Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1578397 [patent_doc_number] => RE037593 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Large scale integrated circuit with sense amplifier circuits for low voltage operation' [patent_app_type] => E1 [patent_app_number] => 09/095101 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 129 [patent_figures_cnt] => 182 [patent_no_of_words] => 59817 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/037/RE037593.pdf [firstpage_image] =>[orig_patent_app_number] => 09095101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095101
Large scale integrated circuit with sense amplifier circuits for low voltage operation Jun 9, 1998 Issued
Array ( [id] => 4096543 [patent_doc_number] => 06026008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Electronic memory device, in particular for use in implantable medical appliances' [patent_app_type] => 1 [patent_app_number] => 9/089449 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2780 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026008.pdf [firstpage_image] =>[orig_patent_app_number] => 089449 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089449
Electronic memory device, in particular for use in implantable medical appliances Jun 2, 1998 Issued
Array ( [id] => 4191743 [patent_doc_number] => 06038160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Ferroelectric semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/981441 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6938 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038160.pdf [firstpage_image] =>[orig_patent_app_number] => 981441 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/981441
Ferroelectric semiconductor memory device May 27, 1998 Issued
Array ( [id] => 3971026 [patent_doc_number] => 05901090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method for erasing flash electrically erasable programmable read-only memory (EEPROM)' [patent_app_type] => 1 [patent_app_number] => 9/085552 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6187 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901090.pdf [firstpage_image] =>[orig_patent_app_number] => 085552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085552
Method for erasing flash electrically erasable programmable read-only memory (EEPROM) May 26, 1998 Issued
Array ( [id] => 3957629 [patent_doc_number] => 05982700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Buffer memory arrays having nonlinear columns for providing parallel data access capability and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 9/082853 [patent_app_country] => US [patent_app_date] => 1998-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 12352 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982700.pdf [firstpage_image] =>[orig_patent_app_number] => 082853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/082853
Buffer memory arrays having nonlinear columns for providing parallel data access capability and methods of operating same May 20, 1998 Issued
Array ( [id] => 4011941 [patent_doc_number] => 05986929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Multi-level nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/080250 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986929.pdf [firstpage_image] =>[orig_patent_app_number] => 080250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080250
Multi-level nonvolatile semiconductor memory device May 17, 1998 Issued
09/079548 SEMICONDUCTOR DEVICE HAVING A LATCH CIRCUIT FOR LATCHING DATA EXTERNALLY INPUT May 14, 1998 Issued
Array ( [id] => 3940174 [patent_doc_number] => 05953261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output' [patent_app_type] => 1 [patent_app_number] => 9/076887 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 56 [patent_no_of_words] => 33158 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953261.pdf [firstpage_image] =>[orig_patent_app_number] => 076887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076887
Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output May 12, 1998 Issued
Array ( [id] => 4140044 [patent_doc_number] => 06128216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'High density planar SRAM cell with merged transistors' [patent_app_type] => 1 [patent_app_number] => 9/076766 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5329 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128216.pdf [firstpage_image] =>[orig_patent_app_number] => 076766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076766
High density planar SRAM cell with merged transistors May 12, 1998 Issued
Array ( [id] => 4204636 [patent_doc_number] => 06044016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Nand-type semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/071770 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3309 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044016.pdf [firstpage_image] =>[orig_patent_app_number] => 071770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071770
Nand-type semiconductor memory device May 3, 1998 Issued
Array ( [id] => 4010912 [patent_doc_number] => 05923614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Structure and method for reading blocks of data from selectable points in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/071144 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5147 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923614.pdf [firstpage_image] =>[orig_patent_app_number] => 071144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071144
Structure and method for reading blocks of data from selectable points in a memory device Apr 29, 1998 Issued
Array ( [id] => 3988732 [patent_doc_number] => 05917764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/069865 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 89 [patent_no_of_words] => 26567 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917764.pdf [firstpage_image] =>[orig_patent_app_number] => 069865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069865
Semiconductor memory device Apr 29, 1998 Issued
Array ( [id] => 4185711 [patent_doc_number] => 06141281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable circuit elements' [patent_app_type] => 1 [patent_app_number] => 9/069468 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141281.pdf [firstpage_image] =>[orig_patent_app_number] => 069468 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069468
Technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable circuit elements Apr 28, 1998 Issued
09/060364 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE AND COMPUTER SYSTEM USING THE SAME Apr 14, 1998 Issued
Array ( [id] => 4327229 [patent_doc_number] => 06243289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Dual floating gate programmable read only memory cell structure and method for its fabrication and operation' [patent_app_type] => 1 [patent_app_number] => 9/056764 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 4736 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243289.pdf [firstpage_image] =>[orig_patent_app_number] => 056764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056764
Dual floating gate programmable read only memory cell structure and method for its fabrication and operation Apr 7, 1998 Issued
Array ( [id] => 4046083 [patent_doc_number] => 05943287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Fault tolerant memory system' [patent_app_type] => 1 [patent_app_number] => 9/052268 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 11919 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943287.pdf [firstpage_image] =>[orig_patent_app_number] => 052268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052268
Fault tolerant memory system Mar 30, 1998 Issued
Array ( [id] => 3940475 [patent_doc_number] => 05953281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Semiconductor memory device having switch to selectively connect output terminal to bit lines' [patent_app_type] => 1 [patent_app_number] => 9/050969 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4019 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953281.pdf [firstpage_image] =>[orig_patent_app_number] => 050969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050969
Semiconductor memory device having switch to selectively connect output terminal to bit lines Mar 30, 1998 Issued
Array ( [id] => 4064388 [patent_doc_number] => 05933379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method and circuit for testing a semiconductor memory device operating at high frequency' [patent_app_type] => 1 [patent_app_number] => 9/052053 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 3368 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933379.pdf [firstpage_image] =>[orig_patent_app_number] => 052053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052053
Method and circuit for testing a semiconductor memory device operating at high frequency Mar 29, 1998 Issued
Array ( [id] => 4251695 [patent_doc_number] => 06091636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Flash memory cell and a new method for sensing the content of the new memory cell' [patent_app_type] => 1 [patent_app_number] => 9/417234 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3897 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091636.pdf [firstpage_image] =>[orig_patent_app_number] => 417234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417234
Flash memory cell and a new method for sensing the content of the new memory cell Mar 25, 1998 Issued
Array ( [id] => 3986500 [patent_doc_number] => 05905679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Semiconductor memory device clamping the overshoot and undershoot of input signal by circuit with PN junction' [patent_app_type] => 1 [patent_app_number] => 9/045567 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 8296 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905679.pdf [firstpage_image] =>[orig_patent_app_number] => 045567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045567
Semiconductor memory device clamping the overshoot and undershoot of input signal by circuit with PN junction Mar 22, 1998 Issued
Menu