Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4017383 [patent_doc_number] => 06005797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Latch-up prevention for memory cells' [patent_app_type] => 1 [patent_app_number] => 9/045465 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8590 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005797.pdf [firstpage_image] =>[orig_patent_app_number] => 045465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045465
Latch-up prevention for memory cells Mar 19, 1998 Issued
Array ( [id] => 3970230 [patent_doc_number] => 05936901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Shared data lines for memory write and memory test operations' [patent_app_type] => 1 [patent_app_number] => 9/044166 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3617 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936901.pdf [firstpage_image] =>[orig_patent_app_number] => 044166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044166
Shared data lines for memory write and memory test operations Mar 18, 1998 Issued
Array ( [id] => 3988462 [patent_doc_number] => 05917745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/040365 [patent_app_country] => US [patent_app_date] => 1998-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7910 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917745.pdf [firstpage_image] =>[orig_patent_app_number] => 040365 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/040365
Semiconductor memory device Mar 17, 1998 Issued
Array ( [id] => 4367976 [patent_doc_number] => 06201743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Semiconductor device having delay circuit for receiving read instruction signal' [patent_app_type] => 1 [patent_app_number] => 9/043151 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9750 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201743.pdf [firstpage_image] =>[orig_patent_app_number] => 043151 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/043151
Semiconductor device having delay circuit for receiving read instruction signal Mar 12, 1998 Issued
Array ( [id] => 3940418 [patent_doc_number] => 05953277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Reference potential generator and a semiconductor memory device having the same' [patent_app_type] => 1 [patent_app_number] => 9/037864 [patent_app_country] => US [patent_app_date] => 1998-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 11566 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953277.pdf [firstpage_image] =>[orig_patent_app_number] => 037864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/037864
Reference potential generator and a semiconductor memory device having the same Mar 9, 1998 Issued
Array ( [id] => 3986626 [patent_doc_number] => 05905688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Auto power down circuit for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/030844 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 55 [patent_no_of_words] => 4960 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905688.pdf [firstpage_image] =>[orig_patent_app_number] => 030844 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030844
Auto power down circuit for a semiconductor memory device Feb 25, 1998 Issued
Array ( [id] => 4246276 [patent_doc_number] => 06075746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'DRAM device with function of producing wordline drive signal based on stored charge in capacitor' [patent_app_type] => 1 [patent_app_number] => 9/030945 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 34 [patent_no_of_words] => 10500 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075746.pdf [firstpage_image] =>[orig_patent_app_number] => 030945 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030945
DRAM device with function of producing wordline drive signal based on stored charge in capacitor Feb 25, 1998 Issued
Array ( [id] => 4026177 [patent_doc_number] => 05963500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/030670 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4243 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963500.pdf [firstpage_image] =>[orig_patent_app_number] => 030670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030670
Semiconductor memory device Feb 24, 1998 Issued
Array ( [id] => 4054553 [patent_doc_number] => 05909407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Word line multi-selection circuit for a memory device' [patent_app_type] => 1 [patent_app_number] => 9/030269 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 14031 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909407.pdf [firstpage_image] =>[orig_patent_app_number] => 030269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030269
Word line multi-selection circuit for a memory device Feb 24, 1998 Issued
Array ( [id] => 3998054 [patent_doc_number] => 05959887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Electrically erasable programmable nonvolatile semiconductor memory having dual operation function' [patent_app_type] => 1 [patent_app_number] => 9/028768 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4706 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959887.pdf [firstpage_image] =>[orig_patent_app_number] => 028768 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/028768
Electrically erasable programmable nonvolatile semiconductor memory having dual operation function Feb 23, 1998 Issued
Array ( [id] => 4025691 [patent_doc_number] => 05963469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Vertical bipolar read access for low voltage memory cell' [patent_app_type] => 1 [patent_app_number] => 9/028249 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3870 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963469.pdf [firstpage_image] =>[orig_patent_app_number] => 028249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/028249
Vertical bipolar read access for low voltage memory cell Feb 23, 1998 Issued
Array ( [id] => 3915431 [patent_doc_number] => 05898632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Sense amplifier of virtual ground flat-cell' [patent_app_type] => 1 [patent_app_number] => 9/026551 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2151 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898632.pdf [firstpage_image] =>[orig_patent_app_number] => 026551 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026551
Sense amplifier of virtual ground flat-cell Feb 19, 1998 Issued
Array ( [id] => 3925252 [patent_doc_number] => 06002622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => 1 [patent_app_number] => 9/026244 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2907 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002622.pdf [firstpage_image] =>[orig_patent_app_number] => 026244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026244
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines Feb 18, 1998 Issued
Array ( [id] => 4144069 [patent_doc_number] => 06034879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Twisted line techniques for multi-gigabit dynamic random access memories' [patent_app_type] => 1 [patent_app_number] => 9/026441 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5871 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034879.pdf [firstpage_image] =>[orig_patent_app_number] => 026441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026441
Twisted line techniques for multi-gigabit dynamic random access memories Feb 18, 1998 Issued
Array ( [id] => 4010621 [patent_doc_number] => 05923594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method and apparatus for coupling data from a memory device using a single ended read data path' [patent_app_type] => 1 [patent_app_number] => 9/024367 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3544 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923594.pdf [firstpage_image] =>[orig_patent_app_number] => 024367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024367
Method and apparatus for coupling data from a memory device using a single ended read data path Feb 16, 1998 Issued
Array ( [id] => 3969888 [patent_doc_number] => 05936877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Die architecture accommodating high-speed semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/023254 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3244 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936877.pdf [firstpage_image] =>[orig_patent_app_number] => 023254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023254
Die architecture accommodating high-speed semiconductor devices Feb 12, 1998 Issued
Array ( [id] => 3936987 [patent_doc_number] => 05946228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Limiting magnetic writing fields to a preferred portion of a changeable magnetic region in magnetic devices' [patent_app_type] => 1 [patent_app_number] => 9/021569 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5215 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946228.pdf [firstpage_image] =>[orig_patent_app_number] => 021569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021569
Limiting magnetic writing fields to a preferred portion of a changeable magnetic region in magnetic devices Feb 9, 1998 Issued
Array ( [id] => 3953590 [patent_doc_number] => 05973986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Memory device including a column decoder for decoding five columns' [patent_app_type] => 1 [patent_app_number] => 9/019264 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3170 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973986.pdf [firstpage_image] =>[orig_patent_app_number] => 019264 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019264
Memory device including a column decoder for decoding five columns Feb 4, 1998 Issued
09/017167 NONVOLATILE MEMORY CONTROL CIRCUIT Feb 1, 1998 Issued
Array ( [id] => 3950613 [patent_doc_number] => 05930181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor memory device with write-switch signal output circuits using complementary write data signals' [patent_app_type] => 1 [patent_app_number] => 9/017470 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930181.pdf [firstpage_image] =>[orig_patent_app_number] => 017470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/017470
Semiconductor memory device with write-switch signal output circuits using complementary write data signals Feb 1, 1998 Issued
Menu