
Son Luu Mai
Examiner (ID: 18155)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818 |
| Total Applications | 3063 |
| Issued Applications | 2917 |
| Pending Applications | 45 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4017383
[patent_doc_number] => 06005797
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[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Latch-up prevention for memory cells'
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[patent_app_number] => 9/045465
[patent_app_country] => US
[patent_app_date] => 1998-03-20
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[pdf_file] => patents/06/005/06005797.pdf
[firstpage_image] =>[orig_patent_app_number] => 045465
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Array
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[patent_issue_date] => 1999-08-10
[patent_title] => 'Shared data lines for memory write and memory test operations'
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Array
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[patent_issue_date] => 1999-06-29
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
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[patent_app_date] => 1998-03-18
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Array
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[patent_issue_date] => 2001-03-13
[patent_title] => 'Semiconductor device having delay circuit for receiving read instruction signal'
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[patent_app_number] => 9/043151
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[patent_app_date] => 1998-03-13
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[pdf_file] => patents/06/201/06201743.pdf
[firstpage_image] =>[orig_patent_app_number] => 043151
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/043151 | Semiconductor device having delay circuit for receiving read instruction signal | Mar 12, 1998 | Issued |
Array
(
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[patent_issue_date] => 1999-09-14
[patent_title] => 'Reference potential generator and a semiconductor memory device having the same'
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Array
(
[id] => 3986626
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[patent_issue_date] => 1999-05-18
[patent_title] => 'Auto power down circuit for a semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/030844 | Auto power down circuit for a semiconductor memory device | Feb 25, 1998 | Issued |
Array
(
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[patent_doc_number] => 06075746
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[patent_issue_date] => 2000-06-13
[patent_title] => 'DRAM device with function of producing wordline drive signal based on stored charge in capacitor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/030945 | DRAM device with function of producing wordline drive signal based on stored charge in capacitor | Feb 25, 1998 | Issued |
Array
(
[id] => 4026177
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[patent_title] => 'Semiconductor memory device'
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[firstpage_image] =>[orig_patent_app_number] => 030670
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/030670 | Semiconductor memory device | Feb 24, 1998 | Issued |
Array
(
[id] => 4054553
[patent_doc_number] => 05909407
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[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Word line multi-selection circuit for a memory device'
[patent_app_type] => 1
[patent_app_number] => 9/030269
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[firstpage_image] =>[orig_patent_app_number] => 030269
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/030269 | Word line multi-selection circuit for a memory device | Feb 24, 1998 | Issued |
Array
(
[id] => 3998054
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[patent_issue_date] => 1999-09-28
[patent_title] => 'Electrically erasable programmable nonvolatile semiconductor memory having dual operation function'
[patent_app_type] => 1
[patent_app_number] => 9/028768
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[pdf_file] => patents/05/959/05959887.pdf
[firstpage_image] =>[orig_patent_app_number] => 028768
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/028768 | Electrically erasable programmable nonvolatile semiconductor memory having dual operation function | Feb 23, 1998 | Issued |
Array
(
[id] => 4025691
[patent_doc_number] => 05963469
[patent_country] => US
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[patent_issue_date] => 1999-10-05
[patent_title] => 'Vertical bipolar read access for low voltage memory cell'
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[firstpage_image] =>[orig_patent_app_number] => 028249
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/028249 | Vertical bipolar read access for low voltage memory cell | Feb 23, 1998 | Issued |
Array
(
[id] => 3915431
[patent_doc_number] => 05898632
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[patent_issue_date] => 1999-04-27
[patent_title] => 'Sense amplifier of virtual ground flat-cell'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/026551 | Sense amplifier of virtual ground flat-cell | Feb 19, 1998 | Issued |
Array
(
[id] => 3925252
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[patent_title] => 'Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines'
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Array
(
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Array
(
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Array
(
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Array
(
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Array
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| 09/017167 | NONVOLATILE MEMORY CONTROL CIRCUIT | Feb 1, 1998 | Issued |
Array
(
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