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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4204828 [patent_doc_number] => 06044029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Device and method for repairing a memory array by storing each bit in multiple memory cells in the array' [patent_app_type] => 1 [patent_app_number] => 9/015543 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8004 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044029.pdf [firstpage_image] =>[orig_patent_app_number] => 015543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015543
Device and method for repairing a memory array by storing each bit in multiple memory cells in the array Jan 28, 1998 Issued
Array ( [id] => 4148040 [patent_doc_number] => 06122213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Device and method for repairing a memory array by storing each bit in multiple memory cells in the array' [patent_app_type] => 1 [patent_app_number] => 9/015541 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8002 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122213.pdf [firstpage_image] =>[orig_patent_app_number] => 015541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015541
Device and method for repairing a memory array by storing each bit in multiple memory cells in the array Jan 28, 1998 Issued
Array ( [id] => 3940254 [patent_doc_number] => 05953266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Device and method for repairing a memory array by storing each bit in multiple memory cells in the array' [patent_app_type] => 1 [patent_app_number] => 9/015542 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7997 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953266.pdf [firstpage_image] =>[orig_patent_app_number] => 015542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015542
Device and method for repairing a memory array by storing each bit in multiple memory cells in the array Jan 28, 1998 Issued
Array ( [id] => 4219189 [patent_doc_number] => 06028792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Multi-level memory for verifying programming results' [patent_app_type] => 1 [patent_app_number] => 9/015611 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 20178 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028792.pdf [firstpage_image] =>[orig_patent_app_number] => 015611 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015611
Multi-level memory for verifying programming results Jan 28, 1998 Issued
Array ( [id] => 4171576 [patent_doc_number] => 06115299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Device and method for repairing a memory array by storing each bit in multiple memory cells in the array' [patent_app_type] => 1 [patent_app_number] => 9/015381 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8017 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115299.pdf [firstpage_image] =>[orig_patent_app_number] => 015381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015381
Device and method for repairing a memory array by storing each bit in multiple memory cells in the array Jan 28, 1998 Issued
Array ( [id] => 4086332 [patent_doc_number] => 05966334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Device and method for repairing a memory array by storing each bit in multiple memory cells in the array' [patent_app_type] => 1 [patent_app_number] => 9/015380 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7996 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966334.pdf [firstpage_image] =>[orig_patent_app_number] => 015380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015380
Device and method for repairing a memory array by storing each bit in multiple memory cells in the array Jan 28, 1998 Issued
Array ( [id] => 4034677 [patent_doc_number] => 05926432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Semiconductor storage device having a hierarchical bit line structure' [patent_app_type] => 1 [patent_app_number] => 9/014528 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7399 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926432.pdf [firstpage_image] =>[orig_patent_app_number] => 014528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014528
Semiconductor storage device having a hierarchical bit line structure Jan 27, 1998 Issued
Array ( [id] => 3950540 [patent_doc_number] => 05930176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Multiple word width memory array clocking scheme' [patent_app_type] => 1 [patent_app_number] => 9/013499 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930176.pdf [firstpage_image] =>[orig_patent_app_number] => 013499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013499
Multiple word width memory array clocking scheme Jan 25, 1998 Issued
Array ( [id] => 3896311 [patent_doc_number] => 05894437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Concurrent read/write architecture for a flash memory' [patent_app_type] => 1 [patent_app_number] => 9/012268 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2345 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894437.pdf [firstpage_image] =>[orig_patent_app_number] => 012268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012268
Concurrent read/write architecture for a flash memory Jan 22, 1998 Issued
Array ( [id] => 4027159 [patent_doc_number] => 05907506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Erasing method and erasing device for non-volatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/008865 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 6783 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907506.pdf [firstpage_image] =>[orig_patent_app_number] => 008865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008865
Erasing method and erasing device for non-volatile semiconductor memory Jan 19, 1998 Issued
Array ( [id] => 4231323 [patent_doc_number] => 06088264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Flash memory partitioning for read-while-write operation' [patent_app_type] => 1 [patent_app_number] => 9/002649 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2475 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088264.pdf [firstpage_image] =>[orig_patent_app_number] => 002649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002649
Flash memory partitioning for read-while-write operation Jan 4, 1998 Issued
Array ( [id] => 4054695 [patent_doc_number] => 05912858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Clock-synchronized input circuit and semiconductor memory device that utilizes same' [patent_app_type] => 1 [patent_app_number] => 9/001649 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6171 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912858.pdf [firstpage_image] =>[orig_patent_app_number] => 001649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001649
Clock-synchronized input circuit and semiconductor memory device that utilizes same Dec 30, 1997 Issued
09/001866 MERGED MEMORY AND LOGIC (MML) INTEGRATED CIRCUITS AND METHODS INCLUDING SERIAL DATA PATH COMPARING Dec 30, 1997 Issued
Array ( [id] => 4034501 [patent_doc_number] => 05926420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Merged Memory and Logic (MML) integrated circuits including data path width reducing circuits and methods' [patent_app_type] => 1 [patent_app_number] => 9/001865 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3933 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926420.pdf [firstpage_image] =>[orig_patent_app_number] => 001865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001865
Merged Memory and Logic (MML) integrated circuits including data path width reducing circuits and methods Dec 30, 1997 Issued
09/001669 ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORY Dec 30, 1997 Issued
Array ( [id] => 4048232 [patent_doc_number] => 05995444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Edge transition detection control of a memory device' [patent_app_type] => 1 [patent_app_number] => 9/000547 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2328 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995444.pdf [firstpage_image] =>[orig_patent_app_number] => 000547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000547
Edge transition detection control of a memory device Dec 29, 1997 Issued
Array ( [id] => 3904880 [patent_doc_number] => 05835407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Flash memory device' [patent_app_type] => 1 [patent_app_number] => 8/998968 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1440 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835407.pdf [firstpage_image] =>[orig_patent_app_number] => 998968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998968
Flash memory device Dec 28, 1997 Issued
Array ( [id] => 3770421 [patent_doc_number] => 05852574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'High density magnetoresistive random access memory device and operating method thereof' [patent_app_type] => 1 [patent_app_number] => 8/998366 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3519 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852574.pdf [firstpage_image] =>[orig_patent_app_number] => 998366 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998366
High density magnetoresistive random access memory device and operating method thereof Dec 23, 1997 Issued
Array ( [id] => 4073345 [patent_doc_number] => 05896331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Reprogrammable addressing process for embedded DRAM' [patent_app_type] => 1 [patent_app_number] => 8/997366 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8892 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896331.pdf [firstpage_image] =>[orig_patent_app_number] => 997366 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997366
Reprogrammable addressing process for embedded DRAM Dec 22, 1997 Issued
Array ( [id] => 4004933 [patent_doc_number] => 05892711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Sector protection circuit for a flash memory device' [patent_app_type] => 1 [patent_app_number] => 8/997250 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3085 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892711.pdf [firstpage_image] =>[orig_patent_app_number] => 997250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997250
Sector protection circuit for a flash memory device Dec 22, 1997 Issued
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