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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3986439 [patent_doc_number] => 05905675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Biasing scheme for reducing stress and improving reliability in EEPROM cells' [patent_app_type] => 1 [patent_app_number] => 8/995870 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4090 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905675.pdf [firstpage_image] =>[orig_patent_app_number] => 995870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995870
Biasing scheme for reducing stress and improving reliability in EEPROM cells Dec 21, 1997 Issued
Array ( [id] => 4086180 [patent_doc_number] => 05966323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Low switching field magnetoresistive tunneling junction for high density arrays' [patent_app_type] => 1 [patent_app_number] => 8/993768 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4759 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966323.pdf [firstpage_image] =>[orig_patent_app_number] => 993768 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993768
Low switching field magnetoresistive tunneling junction for high density arrays Dec 17, 1997 Issued
Array ( [id] => 4015097 [patent_doc_number] => 05859796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Programming of memory cells using connected floating gate analog reference cell' [patent_app_type] => 1 [patent_app_number] => 8/991466 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2695 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859796.pdf [firstpage_image] =>[orig_patent_app_number] => 991466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991466
Programming of memory cells using connected floating gate analog reference cell Dec 15, 1997 Issued
Array ( [id] => 4034646 [patent_doc_number] => 05926430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Semiconductor integrated circuit device and method of activating the same' [patent_app_type] => 1 [patent_app_number] => 8/985425 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 20092 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926430.pdf [firstpage_image] =>[orig_patent_app_number] => 985425 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985425
Semiconductor integrated circuit device and method of activating the same Dec 4, 1997 Issued
Array ( [id] => 3802245 [patent_doc_number] => 05841691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Adjustable cell plate generator' [patent_app_type] => 1 [patent_app_number] => 8/979403 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4137 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841691.pdf [firstpage_image] =>[orig_patent_app_number] => 979403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979403
Adjustable cell plate generator Nov 25, 1997 Issued
Array ( [id] => 3980904 [patent_doc_number] => 05886949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Method and circuit for generating a synchronizing ATD signal' [patent_app_type] => 1 [patent_app_number] => 8/978665 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886949.pdf [firstpage_image] =>[orig_patent_app_number] => 978665 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978665
Method and circuit for generating a synchronizing ATD signal Nov 25, 1997 Issued
Array ( [id] => 4038618 [patent_doc_number] => 05903504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Op amp circuit with variable resistance and memory system including same' [patent_app_type] => 1 [patent_app_number] => 8/978734 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 13624 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903504.pdf [firstpage_image] =>[orig_patent_app_number] => 978734 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978734
Op amp circuit with variable resistance and memory system including same Nov 25, 1997 Issued
Array ( [id] => 4027200 [patent_doc_number] => 05907509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Semiconductor memory device that can read out data at high speed' [patent_app_type] => 1 [patent_app_number] => 8/978421 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 17183 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907509.pdf [firstpage_image] =>[orig_patent_app_number] => 978421 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978421
Semiconductor memory device that can read out data at high speed Nov 24, 1997 Issued
Array ( [id] => 4209485 [patent_doc_number] => 06014340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence' [patent_app_type] => 1 [patent_app_number] => 8/978440 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 9864 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014340.pdf [firstpage_image] =>[orig_patent_app_number] => 978440 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978440
Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence Nov 24, 1997 Issued
Array ( [id] => 3824952 [patent_doc_number] => 05812460 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Nonvolatile semiconductor memory device having test circuit for testing erasing function thereof' [patent_app_type] => 1 [patent_app_number] => 8/974670 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4640 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812460.pdf [firstpage_image] =>[orig_patent_app_number] => 974670 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974670
Nonvolatile semiconductor memory device having test circuit for testing erasing function thereof Nov 18, 1997 Issued
Array ( [id] => 4265768 [patent_doc_number] => 06208545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Three dimensional structure memory' [patent_app_type] => 1 [patent_app_number] => 8/971367 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7176 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208545.pdf [firstpage_image] =>[orig_patent_app_number] => 971367 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971367
Three dimensional structure memory Nov 16, 1997 Issued
Array ( [id] => 3969931 [patent_doc_number] => 05936880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Bi-layer programmable resistor memory' [patent_app_type] => 1 [patent_app_number] => 8/969567 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3454 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936880.pdf [firstpage_image] =>[orig_patent_app_number] => 969567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969567
Bi-layer programmable resistor memory Nov 12, 1997 Issued
Array ( [id] => 3915316 [patent_doc_number] => 05898624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Noise restraining semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/969466 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1355 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898624.pdf [firstpage_image] =>[orig_patent_app_number] => 969466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969466
Noise restraining semiconductor memory device Nov 12, 1997 Issued
Array ( [id] => 3905179 [patent_doc_number] => 05835426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Redundant circuit' [patent_app_type] => 1 [patent_app_number] => 8/968068 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835426.pdf [firstpage_image] =>[orig_patent_app_number] => 968068 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968068
Redundant circuit Nov 11, 1997 Issued
Array ( [id] => 4169905 [patent_doc_number] => 06104627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/967235 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3393 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104627.pdf [firstpage_image] =>[orig_patent_app_number] => 967235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967235
Semiconductor memory device Nov 4, 1997 Issued
Array ( [id] => 3816020 [patent_doc_number] => 05854762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Protection circuit for redundancy register set-up cells of electrically programmable non-volatile memory devices' [patent_app_type] => 1 [patent_app_number] => 8/961368 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4225 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854762.pdf [firstpage_image] =>[orig_patent_app_number] => 961368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961368
Protection circuit for redundancy register set-up cells of electrically programmable non-volatile memory devices Oct 29, 1997 Issued
Array ( [id] => 3993960 [patent_doc_number] => 05862090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Semiconductor memory device having cell array divided into a plurality of cell blocks' [patent_app_type] => 1 [patent_app_number] => 8/959466 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7456 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862090.pdf [firstpage_image] =>[orig_patent_app_number] => 959466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959466
Semiconductor memory device having cell array divided into a plurality of cell blocks Oct 27, 1997 Issued
Array ( [id] => 4061129 [patent_doc_number] => 05870336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Memory with improved reading time' [patent_app_type] => 1 [patent_app_number] => 8/957666 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4742 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870336.pdf [firstpage_image] =>[orig_patent_app_number] => 957666 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957666
Memory with improved reading time Oct 23, 1997 Issued
Array ( [id] => 3950741 [patent_doc_number] => 05930190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Single-chip memory system and method for operating the same' [patent_app_type] => 1 [patent_app_number] => 8/956369 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4651 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930190.pdf [firstpage_image] =>[orig_patent_app_number] => 956369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956369
Single-chip memory system and method for operating the same Oct 22, 1997 Issued
Array ( [id] => 3948561 [patent_doc_number] => 05872731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Multi-state Josephson memory' [patent_app_type] => 1 [patent_app_number] => 8/948570 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4994 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872731.pdf [firstpage_image] =>[orig_patent_app_number] => 948570 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948570
Multi-state Josephson memory Oct 9, 1997 Issued
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