Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4169905 [patent_doc_number] => 06104627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/967235 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3393 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104627.pdf [firstpage_image] =>[orig_patent_app_number] => 967235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967235
Semiconductor memory device Nov 4, 1997 Issued
Array ( [id] => 3816020 [patent_doc_number] => 05854762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Protection circuit for redundancy register set-up cells of electrically programmable non-volatile memory devices' [patent_app_type] => 1 [patent_app_number] => 8/961368 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4225 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854762.pdf [firstpage_image] =>[orig_patent_app_number] => 961368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961368
Protection circuit for redundancy register set-up cells of electrically programmable non-volatile memory devices Oct 29, 1997 Issued
Array ( [id] => 3993960 [patent_doc_number] => 05862090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Semiconductor memory device having cell array divided into a plurality of cell blocks' [patent_app_type] => 1 [patent_app_number] => 8/959466 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7456 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862090.pdf [firstpage_image] =>[orig_patent_app_number] => 959466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959466
Semiconductor memory device having cell array divided into a plurality of cell blocks Oct 27, 1997 Issued
Array ( [id] => 4061129 [patent_doc_number] => 05870336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Memory with improved reading time' [patent_app_type] => 1 [patent_app_number] => 8/957666 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4742 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870336.pdf [firstpage_image] =>[orig_patent_app_number] => 957666 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957666
Memory with improved reading time Oct 23, 1997 Issued
Array ( [id] => 3950741 [patent_doc_number] => 05930190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Single-chip memory system and method for operating the same' [patent_app_type] => 1 [patent_app_number] => 8/956369 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4651 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930190.pdf [firstpage_image] =>[orig_patent_app_number] => 956369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956369
Single-chip memory system and method for operating the same Oct 22, 1997 Issued
Array ( [id] => 3948561 [patent_doc_number] => 05872731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Multi-state Josephson memory' [patent_app_type] => 1 [patent_app_number] => 8/948570 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4994 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872731.pdf [firstpage_image] =>[orig_patent_app_number] => 948570 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948570
Multi-state Josephson memory Oct 9, 1997 Issued
Array ( [id] => 4034575 [patent_doc_number] => 05926425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Memory with bit line discharge circuit elements' [patent_app_type] => 1 [patent_app_number] => 8/941564 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4565 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926425.pdf [firstpage_image] =>[orig_patent_app_number] => 941564 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941564
Memory with bit line discharge circuit elements Sep 29, 1997 Issued
Array ( [id] => 3970917 [patent_doc_number] => 05901084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Nonvolatile semiconductor memory device having floating gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/933764 [patent_app_country] => US [patent_app_date] => 1997-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7629 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901084.pdf [firstpage_image] =>[orig_patent_app_number] => 933764 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933764
Nonvolatile semiconductor memory device having floating gate electrode Sep 22, 1997 Issued
Array ( [id] => 3957075 [patent_doc_number] => 05982662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor memory device with improved read characteristics for data having multi values' [patent_app_type] => 1 [patent_app_number] => 8/920366 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15310 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982662.pdf [firstpage_image] =>[orig_patent_app_number] => 920366 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920366
Semiconductor memory device with improved read characteristics for data having multi values Aug 28, 1997 Issued
Array ( [id] => 3802747 [patent_doc_number] => 05841725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Charge pump circuit for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/918667 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 5424 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841725.pdf [firstpage_image] =>[orig_patent_app_number] => 918667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918667
Charge pump circuit for a semiconductor memory device Aug 27, 1997 Issued
Array ( [id] => 3802553 [patent_doc_number] => 05841711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Semiconductor memory device with redundancy switching method' [patent_app_type] => 1 [patent_app_number] => 8/918668 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6194 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841711.pdf [firstpage_image] =>[orig_patent_app_number] => 918668 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918668
Semiconductor memory device with redundancy switching method Aug 27, 1997 Issued
Array ( [id] => 3825325 [patent_doc_number] => 05812491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Mode register control circuit and semiconductor device having the same' [patent_app_type] => 1 [patent_app_number] => 8/916201 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6389 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812491.pdf [firstpage_image] =>[orig_patent_app_number] => 916201 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916201
Mode register control circuit and semiconductor device having the same Aug 21, 1997 Issued
Array ( [id] => 3950626 [patent_doc_number] => 05930182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Adjustable delay circuit for setting the speed grade of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/917651 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2874 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930182.pdf [firstpage_image] =>[orig_patent_app_number] => 917651 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917651
Adjustable delay circuit for setting the speed grade of a semiconductor device Aug 21, 1997 Issued
Array ( [id] => 3953631 [patent_doc_number] => 05973989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method and apparatus for transmitting and receiving data at both the rising edge and the falling edge of a clock signal' [patent_app_type] => 1 [patent_app_number] => 8/918568 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 57 [patent_no_of_words] => 7776 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973989.pdf [firstpage_image] =>[orig_patent_app_number] => 918568 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918568
Method and apparatus for transmitting and receiving data at both the rising edge and the falling edge of a clock signal Aug 21, 1997 Issued
Array ( [id] => 3947391 [patent_doc_number] => 05940343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Memory sub-word line driver operated by unboosted voltage' [patent_app_type] => 1 [patent_app_number] => 8/924465 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4006 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940343.pdf [firstpage_image] =>[orig_patent_app_number] => 924465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924465
Memory sub-word line driver operated by unboosted voltage Aug 20, 1997 Issued
Array ( [id] => 3896486 [patent_doc_number] => 05894449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Equalization signal generator for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/915567 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 30 [patent_no_of_words] => 2519 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894449.pdf [firstpage_image] =>[orig_patent_app_number] => 915567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915567
Equalization signal generator for semiconductor memory device Aug 20, 1997 Issued
Array ( [id] => 4064340 [patent_doc_number] => 05933377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Semiconductor memory device and defect repair method for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/915270 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 13620 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933377.pdf [firstpage_image] =>[orig_patent_app_number] => 915270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915270
Semiconductor memory device and defect repair method for semiconductor memory device Aug 19, 1997 Issued
Array ( [id] => 3756722 [patent_doc_number] => 05801994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Non-volatile memory array architecture' [patent_app_type] => 1 [patent_app_number] => 8/911968 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4794 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801994.pdf [firstpage_image] =>[orig_patent_app_number] => 911968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911968
Non-volatile memory array architecture Aug 14, 1997 Issued
Array ( [id] => 4073384 [patent_doc_number] => 05896334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Circuit and method for memory device with defect current isolation' [patent_app_type] => 1 [patent_app_number] => 8/911667 [patent_app_country] => US [patent_app_date] => 1997-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5603 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896334.pdf [firstpage_image] =>[orig_patent_app_number] => 911667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911667
Circuit and method for memory device with defect current isolation Aug 13, 1997 Issued
Array ( [id] => 4004919 [patent_doc_number] => 05892710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and circuitry for storing discrete amounts of charge in a single memory element' [patent_app_type] => 1 [patent_app_number] => 8/910866 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7138 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892710.pdf [firstpage_image] =>[orig_patent_app_number] => 910866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910866
Method and circuitry for storing discrete amounts of charge in a single memory element Aug 12, 1997 Issued
Menu