
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3957075
[patent_doc_number] => 05982662
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Semiconductor memory device with improved read characteristics for data having multi values'
[patent_app_type] => 1
[patent_app_number] => 8/920366
[patent_app_country] => US
[patent_app_date] => 1997-08-29
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Array
(
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[patent_issue_date] => 1998-11-24
[patent_title] => 'Semiconductor memory device with redundancy switching method'
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[patent_app_number] => 8/918668
[patent_app_country] => US
[patent_app_date] => 1997-08-28
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Array
(
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[patent_issue_date] => 1998-11-24
[patent_title] => 'Charge pump circuit for a semiconductor memory device'
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[patent_app_number] => 8/918667
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/918667 | Charge pump circuit for a semiconductor memory device | Aug 27, 1997 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Adjustable delay circuit for setting the speed grade of a semiconductor device'
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Array
(
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[patent_issue_date] => 1999-10-26
[patent_title] => 'Method and apparatus for transmitting and receiving data at both the rising edge and the falling edge of a clock signal'
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Array
(
[id] => 3825325
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[patent_issue_date] => 1998-09-22
[patent_title] => 'Mode register control circuit and semiconductor device having the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/916201 | Mode register control circuit and semiconductor device having the same | Aug 21, 1997 | Issued |
Array
(
[id] => 3896486
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[patent_issue_date] => 1999-04-13
[patent_title] => 'Equalization signal generator for semiconductor memory device'
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Array
(
[id] => 3947391
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[patent_issue_date] => 1999-08-17
[patent_title] => 'Memory sub-word line driver operated by unboosted voltage'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/924465 | Memory sub-word line driver operated by unboosted voltage | Aug 20, 1997 | Issued |
Array
(
[id] => 4064340
[patent_doc_number] => 05933377
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[patent_issue_date] => 1999-08-03
[patent_title] => 'Semiconductor memory device and defect repair method for semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/915270 | Semiconductor memory device and defect repair method for semiconductor memory device | Aug 19, 1997 | Issued |
Array
(
[id] => 3756722
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[patent_title] => 'Non-volatile memory array architecture'
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[patent_app_number] => 8/911968
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/911968 | Non-volatile memory array architecture | Aug 14, 1997 | Issued |
Array
(
[id] => 4073384
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/911667 | Circuit and method for memory device with defect current isolation | Aug 13, 1997 | Issued |
Array
(
[id] => 4004919
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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