Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4067296 [patent_doc_number] => 05864505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Random access memory with plural simultaneously operable banks' [patent_app_type] => 1 [patent_app_number] => 8/893568 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2578 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864505.pdf [firstpage_image] =>[orig_patent_app_number] => 893568 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893568
Random access memory with plural simultaneously operable banks Jul 10, 1997 Issued
Array ( [id] => 3873323 [patent_doc_number] => 05796661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Output buffer circuit of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/890025 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 19 [patent_no_of_words] => 3764 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796661.pdf [firstpage_image] =>[orig_patent_app_number] => 890025 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890025
Output buffer circuit of semiconductor memory device Jul 9, 1997 Issued
Array ( [id] => 4004974 [patent_doc_number] => 05892714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method of programming and/or verifying a threshold voltage level of a nonvolatile memory cell' [patent_app_type] => 1 [patent_app_number] => 8/890564 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 7366 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892714.pdf [firstpage_image] =>[orig_patent_app_number] => 890564 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890564
Method of programming and/or verifying a threshold voltage level of a nonvolatile memory cell Jul 8, 1997 Issued
Array ( [id] => 4027318 [patent_doc_number] => 05907516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Semiconductor memory device with reduced data bus line load' [patent_app_type] => 1 [patent_app_number] => 8/889332 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3260 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907516.pdf [firstpage_image] =>[orig_patent_app_number] => 889332 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889332
Semiconductor memory device with reduced data bus line load Jul 7, 1997 Issued
Array ( [id] => 3905383 [patent_doc_number] => 05835439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Sub word line driving circuit and a semiconductor memory device using the same' [patent_app_type] => 1 [patent_app_number] => 8/887280 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2850 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835439.pdf [firstpage_image] =>[orig_patent_app_number] => 887280 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/887280
Sub word line driving circuit and a semiconductor memory device using the same Jul 1, 1997 Issued
Array ( [id] => 3891617 [patent_doc_number] => 05798960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Current memory for sampling analog currents' [patent_app_type] => 1 [patent_app_number] => 8/884975 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798960.pdf [firstpage_image] =>[orig_patent_app_number] => 884975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884975
Current memory for sampling analog currents Jun 29, 1997 Issued
Array ( [id] => 3824813 [patent_doc_number] => 05812452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Electrically byte-selectable and byte-alterable memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/884825 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 6945 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812452.pdf [firstpage_image] =>[orig_patent_app_number] => 884825 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884825
Electrically byte-selectable and byte-alterable memory arrays Jun 29, 1997 Issued
Array ( [id] => 3853621 [patent_doc_number] => 05848003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/884265 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7931 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848003.pdf [firstpage_image] =>[orig_patent_app_number] => 884265 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884265
Semiconductor memory Jun 26, 1997 Issued
Array ( [id] => 3939714 [patent_doc_number] => 05877979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Single-sided RAM cell and method of accessing same' [patent_app_type] => 1 [patent_app_number] => 8/884369 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4235 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877979.pdf [firstpage_image] =>[orig_patent_app_number] => 884369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884369
Single-sided RAM cell and method of accessing same Jun 25, 1997 Issued
Array ( [id] => 3826239 [patent_doc_number] => 05771201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Synchronous semiconductor device having an apparatus for producing strobe clock signals' [patent_app_type] => 1 [patent_app_number] => 8/882864 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2667 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771201.pdf [firstpage_image] =>[orig_patent_app_number] => 882864 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882864
Synchronous semiconductor device having an apparatus for producing strobe clock signals Jun 25, 1997 Issued
Array ( [id] => 3853444 [patent_doc_number] => 05847992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Multi-level non-volatile semiconductor memory device having improved multi-level data storing circuits' [patent_app_type] => 1 [patent_app_number] => 8/883370 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 25257 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847992.pdf [firstpage_image] =>[orig_patent_app_number] => 883370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883370
Multi-level non-volatile semiconductor memory device having improved multi-level data storing circuits Jun 25, 1997 Issued
Array ( [id] => 3853468 [patent_doc_number] => 05847993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Non-volatile programmable CMOS logic cell and method of operating same' [patent_app_type] => 1 [patent_app_number] => 8/881719 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847993.pdf [firstpage_image] =>[orig_patent_app_number] => 881719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881719
Non-volatile programmable CMOS logic cell and method of operating same Jun 22, 1997 Issued
Array ( [id] => 3770500 [patent_doc_number] => 05852579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory' [patent_app_type] => 1 [patent_app_number] => 8/878904 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4498 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852579.pdf [firstpage_image] =>[orig_patent_app_number] => 878904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878904
Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory Jun 18, 1997 Issued
Array ( [id] => 4064171 [patent_doc_number] => 05933365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Memory element with energy control mechanism' [patent_app_type] => 1 [patent_app_number] => 8/878870 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 11023 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933365.pdf [firstpage_image] =>[orig_patent_app_number] => 878870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878870
Memory element with energy control mechanism Jun 18, 1997 Issued
Array ( [id] => 3915342 [patent_doc_number] => 05898626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Redundancy programming circuit and system for semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/879208 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898626.pdf [firstpage_image] =>[orig_patent_app_number] => 879208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879208
Redundancy programming circuit and system for semiconductor memory Jun 18, 1997 Issued
Array ( [id] => 3892078 [patent_doc_number] => 05805500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Circuit and method for generating a read reference signal for nonvolatile memory cells' [patent_app_type] => 1 [patent_app_number] => 8/877921 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5585 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805500.pdf [firstpage_image] =>[orig_patent_app_number] => 877921 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877921
Circuit and method for generating a read reference signal for nonvolatile memory cells Jun 17, 1997 Issued
Array ( [id] => 3980551 [patent_doc_number] => 05886925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Read circuit and method for nonvolatile memory cells with an equalizing structure' [patent_app_type] => 1 [patent_app_number] => 8/877922 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5711 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886925.pdf [firstpage_image] =>[orig_patent_app_number] => 877922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877922
Read circuit and method for nonvolatile memory cells with an equalizing structure Jun 17, 1997 Issued
Array ( [id] => 4054735 [patent_doc_number] => 05875142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Integrated circuit with temperature detector' [patent_app_type] => 1 [patent_app_number] => 8/877229 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3223 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875142.pdf [firstpage_image] =>[orig_patent_app_number] => 877229 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877229
Integrated circuit with temperature detector Jun 16, 1997 Issued
Array ( [id] => 3937136 [patent_doc_number] => 05946238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Single-cell reference signal generating circuit for reading nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 8/877066 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946238.pdf [firstpage_image] =>[orig_patent_app_number] => 877066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877066
Single-cell reference signal generating circuit for reading nonvolatile memory Jun 16, 1997 Issued
Array ( [id] => 4015067 [patent_doc_number] => 05859794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Multilevel memory cell sense amplifier system and sensing methods' [patent_app_type] => 1 [patent_app_number] => 8/874794 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6297 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859794.pdf [firstpage_image] =>[orig_patent_app_number] => 874794 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874794
Multilevel memory cell sense amplifier system and sensing methods Jun 12, 1997 Issued
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