Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4025608 [patent_doc_number] => 05963463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method for on-board programming of PRD serial EEPROMS' [patent_app_type] => 1 [patent_app_number] => 8/873971 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2887 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963463.pdf [firstpage_image] =>[orig_patent_app_number] => 873971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873971
Method for on-board programming of PRD serial EEPROMS Jun 11, 1997 Issued
Array ( [id] => 3853785 [patent_doc_number] => 05848014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Semiconductor device such as a static random access memory (SRAM) having a low power mode using a clock disable circuit' [patent_app_type] => 1 [patent_app_number] => 8/874006 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4531 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848014.pdf [firstpage_image] =>[orig_patent_app_number] => 874006 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874006
Semiconductor device such as a static random access memory (SRAM) having a low power mode using a clock disable circuit Jun 11, 1997 Issued
Array ( [id] => 4015040 [patent_doc_number] => 05859792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Circuit for on-board programming of PRD serial EEPROMs' [patent_app_type] => 1 [patent_app_number] => 8/873968 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2781 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859792.pdf [firstpage_image] =>[orig_patent_app_number] => 873968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873968
Circuit for on-board programming of PRD serial EEPROMs Jun 11, 1997 Issued
Array ( [id] => 4077899 [patent_doc_number] => 05867448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Buffer for memory modules with trace delay compensation' [patent_app_type] => 1 [patent_app_number] => 8/873005 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867448.pdf [firstpage_image] =>[orig_patent_app_number] => 873005 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873005
Buffer for memory modules with trace delay compensation Jun 10, 1997 Issued
Array ( [id] => 3844741 [patent_doc_number] => 05761142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Semiconductor memory device having sense amplifier drivers disposed on center portion of cell array block' [patent_app_type] => 1 [patent_app_number] => 8/871132 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3645 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761142.pdf [firstpage_image] =>[orig_patent_app_number] => 871132 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871132
Semiconductor memory device having sense amplifier drivers disposed on center portion of cell array block Jun 5, 1997 Issued
Array ( [id] => 3837759 [patent_doc_number] => 05784326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Voltage raising device' [patent_app_type] => 1 [patent_app_number] => 8/868731 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3573 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784326.pdf [firstpage_image] =>[orig_patent_app_number] => 868731 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868731
Voltage raising device Jun 3, 1997 Issued
Array ( [id] => 4034603 [patent_doc_number] => 05926427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Power line noise prevention circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/869005 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5187 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926427.pdf [firstpage_image] =>[orig_patent_app_number] => 869005 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869005
Power line noise prevention circuit for semiconductor memory device Jun 3, 1997 Issued
Array ( [id] => 4067265 [patent_doc_number] => 05864503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Method for verifying electrically programmable non-volatile memory cells of an electrically programmable non-volatile memory device after programming' [patent_app_type] => 1 [patent_app_number] => 8/866531 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5782 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864503.pdf [firstpage_image] =>[orig_patent_app_number] => 866531 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866531
Method for verifying electrically programmable non-volatile memory cells of an electrically programmable non-volatile memory device after programming May 29, 1997 Issued
Array ( [id] => 3802300 [patent_doc_number] => 05841695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell' [patent_app_type] => 1 [patent_app_number] => 8/865470 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841695.pdf [firstpage_image] =>[orig_patent_app_number] => 865470 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865470
Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell May 28, 1997 Issued
Array ( [id] => 3994085 [patent_doc_number] => 05949724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Burn-in stress circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/858769 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4966 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949724.pdf [firstpage_image] =>[orig_patent_app_number] => 858769 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858769
Burn-in stress circuit for semiconductor memory device May 18, 1997 Issued
Array ( [id] => 3892153 [patent_doc_number] => 05805506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Semiconductor device having a latch circuit for latching data externally input' [patent_app_type] => 1 [patent_app_number] => 8/857828 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 4709 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805506.pdf [firstpage_image] =>[orig_patent_app_number] => 857828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857828
Semiconductor device having a latch circuit for latching data externally input May 15, 1997 Issued
Array ( [id] => 3904764 [patent_doc_number] => 05835399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Imprint compensation circuit for use in ferroelectric semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/857469 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2892 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835399.pdf [firstpage_image] =>[orig_patent_app_number] => 857469 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857469
Imprint compensation circuit for use in ferroelectric semiconductor memory device May 14, 1997 Issued
Array ( [id] => 3900945 [patent_doc_number] => 05777941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Column multiplexer' [patent_app_type] => 1 [patent_app_number] => 8/853732 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2381 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777941.pdf [firstpage_image] =>[orig_patent_app_number] => 853732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853732
Column multiplexer May 8, 1997 Issued
Array ( [id] => 3867049 [patent_doc_number] => 05768203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Single-chip memory system having a page access mode' [patent_app_type] => 1 [patent_app_number] => 8/839130 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768203.pdf [firstpage_image] =>[orig_patent_app_number] => 839130 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839130
Single-chip memory system having a page access mode Apr 22, 1997 Issued
Array ( [id] => 3826113 [patent_doc_number] => 05771191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Method and system for inspecting semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/838984 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5012 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771191.pdf [firstpage_image] =>[orig_patent_app_number] => 838984 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838984
Method and system for inspecting semiconductor memory device Apr 22, 1997 Issued
Array ( [id] => 3971180 [patent_doc_number] => 05901100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'First-in, first-out integrated circuit memory device utilizing a dynamic random access memory array for data storage implemented in conjunction with an associated static random access memory cache' [patent_app_type] => 1 [patent_app_number] => 8/840118 [patent_app_country] => US [patent_app_date] => 1997-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8797 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901100.pdf [firstpage_image] =>[orig_patent_app_number] => 840118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840118
First-in, first-out integrated circuit memory device utilizing a dynamic random access memory array for data storage implemented in conjunction with an associated static random access memory cache Mar 31, 1997 Issued
Array ( [id] => 4077522 [patent_doc_number] => 05867424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Memory array having a reduced number of metal source lines' [patent_app_type] => 1 [patent_app_number] => 8/829602 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867424.pdf [firstpage_image] =>[orig_patent_app_number] => 829602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829602
Memory array having a reduced number of metal source lines Mar 30, 1997 Issued
Array ( [id] => 3807836 [patent_doc_number] => 05781482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/829284 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4372 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781482.pdf [firstpage_image] =>[orig_patent_app_number] => 829284 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829284
Semiconductor memory device Mar 30, 1997 Issued
Array ( [id] => 3753382 [patent_doc_number] => 05754483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Reference word line and data propagation reproduction circuit for memories provided with hierarchical decoders' [patent_app_type] => 1 [patent_app_number] => 8/835033 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4616 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754483.pdf [firstpage_image] =>[orig_patent_app_number] => 835033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835033
Reference word line and data propagation reproduction circuit for memories provided with hierarchical decoders Mar 26, 1997 Issued
Array ( [id] => 4045593 [patent_doc_number] => 05856943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Scalable flash EEPROM memory cell and array' [patent_app_type] => 1 [patent_app_number] => 8/824629 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8582 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856943.pdf [firstpage_image] =>[orig_patent_app_number] => 824629 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824629
Scalable flash EEPROM memory cell and array Mar 26, 1997 Issued
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