| Application number | Title of the application | Filing Date | Status |
|---|
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[patent_issue_date] => 1999-11-09
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[patent_issue_date] => 1999-05-11
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| 08/814881 | SEMICONDUCTOR MEMORY DEVICE | Mar 11, 1997 | Abandoned |
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Array
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Array
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[id] => 3826064
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Array
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Array
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| 08/782587 | METHOD FOR PROGRAMMING A SINGLE EPROM OR FLASH MEMORY CELL TO STORE MULTIPLE BITS OF DATA THAT UTILIZES A PUNCHTHROUGH CURRENT | Jan 12, 1997 | Abandoned |
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