Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3900945 [patent_doc_number] => 05777941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Column multiplexer' [patent_app_type] => 1 [patent_app_number] => 8/853732 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2381 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777941.pdf [firstpage_image] =>[orig_patent_app_number] => 853732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853732
Column multiplexer May 8, 1997 Issued
Array ( [id] => 3826113 [patent_doc_number] => 05771191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Method and system for inspecting semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/838984 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5012 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771191.pdf [firstpage_image] =>[orig_patent_app_number] => 838984 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838984
Method and system for inspecting semiconductor memory device Apr 22, 1997 Issued
Array ( [id] => 3867049 [patent_doc_number] => 05768203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Single-chip memory system having a page access mode' [patent_app_type] => 1 [patent_app_number] => 8/839130 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768203.pdf [firstpage_image] =>[orig_patent_app_number] => 839130 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839130
Single-chip memory system having a page access mode Apr 22, 1997 Issued
Array ( [id] => 3971180 [patent_doc_number] => 05901100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'First-in, first-out integrated circuit memory device utilizing a dynamic random access memory array for data storage implemented in conjunction with an associated static random access memory cache' [patent_app_type] => 1 [patent_app_number] => 8/840118 [patent_app_country] => US [patent_app_date] => 1997-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8797 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901100.pdf [firstpage_image] =>[orig_patent_app_number] => 840118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840118
First-in, first-out integrated circuit memory device utilizing a dynamic random access memory array for data storage implemented in conjunction with an associated static random access memory cache Mar 31, 1997 Issued
Array ( [id] => 4077522 [patent_doc_number] => 05867424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Memory array having a reduced number of metal source lines' [patent_app_type] => 1 [patent_app_number] => 8/829602 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867424.pdf [firstpage_image] =>[orig_patent_app_number] => 829602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829602
Memory array having a reduced number of metal source lines Mar 30, 1997 Issued
Array ( [id] => 3807836 [patent_doc_number] => 05781482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/829284 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4372 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781482.pdf [firstpage_image] =>[orig_patent_app_number] => 829284 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829284
Semiconductor memory device Mar 30, 1997 Issued
Array ( [id] => 3753382 [patent_doc_number] => 05754483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Reference word line and data propagation reproduction circuit for memories provided with hierarchical decoders' [patent_app_type] => 1 [patent_app_number] => 8/835033 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4616 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754483.pdf [firstpage_image] =>[orig_patent_app_number] => 835033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835033
Reference word line and data propagation reproduction circuit for memories provided with hierarchical decoders Mar 26, 1997 Issued
Array ( [id] => 3756651 [patent_doc_number] => 05801988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Circuit for the generation of a voltage as a function of the conductivity of an elementary cell of a non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/835031 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4514 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801988.pdf [firstpage_image] =>[orig_patent_app_number] => 835031 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835031
Circuit for the generation of a voltage as a function of the conductivity of an elementary cell of a non-volatile memory Mar 26, 1997 Issued
Array ( [id] => 4045593 [patent_doc_number] => 05856943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Scalable flash EEPROM memory cell and array' [patent_app_type] => 1 [patent_app_number] => 8/824629 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8582 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856943.pdf [firstpage_image] =>[orig_patent_app_number] => 824629 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824629
Scalable flash EEPROM memory cell and array Mar 26, 1997 Issued
Array ( [id] => 3939725 [patent_doc_number] => 05877980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Nonvolatile memory device having a program-assist plate' [patent_app_type] => 1 [patent_app_number] => 8/824483 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 9632 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877980.pdf [firstpage_image] =>[orig_patent_app_number] => 824483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824483
Nonvolatile memory device having a program-assist plate Mar 25, 1997 Issued
Array ( [id] => 3957644 [patent_doc_number] => 05982701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor memory device with reduced inter-band tunnel current' [patent_app_type] => 1 [patent_app_number] => 8/822981 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5631 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982701.pdf [firstpage_image] =>[orig_patent_app_number] => 822981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822981
Semiconductor memory device with reduced inter-band tunnel current Mar 20, 1997 Issued
Array ( [id] => 4038482 [patent_doc_number] => 05903495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Semiconductor device and memory system' [patent_app_type] => 1 [patent_app_number] => 8/819484 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 100 [patent_figures_cnt] => 175 [patent_no_of_words] => 59688 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903495.pdf [firstpage_image] =>[orig_patent_app_number] => 819484 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/819484
Semiconductor device and memory system Mar 16, 1997 Issued
08/814881 SEMICONDUCTOR MEMORY DEVICE Mar 11, 1997 Abandoned
Array ( [id] => 3956987 [patent_doc_number] => 05982656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method and apparatus for checking the resistance of programmable elements' [patent_app_type] => 1 [patent_app_number] => 8/813767 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3523 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982656.pdf [firstpage_image] =>[orig_patent_app_number] => 813767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813767
Method and apparatus for checking the resistance of programmable elements Mar 6, 1997 Issued
Array ( [id] => 3802314 [patent_doc_number] => 05841696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path' [patent_app_type] => 1 [patent_app_number] => 8/811683 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9277 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841696.pdf [firstpage_image] =>[orig_patent_app_number] => 811683 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/811683
Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path Mar 4, 1997 Issued
Array ( [id] => 3882980 [patent_doc_number] => 05838622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Reconfigurable multiplexed address scheme for asymmetrically addressed DRAMs' [patent_app_type] => 1 [patent_app_number] => 8/850933 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3741 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838622.pdf [firstpage_image] =>[orig_patent_app_number] => 850933 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850933
Reconfigurable multiplexed address scheme for asymmetrically addressed DRAMs Feb 27, 1997 Issued
Array ( [id] => 3851996 [patent_doc_number] => 05708611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/801889 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 10754 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708611.pdf [firstpage_image] =>[orig_patent_app_number] => 801889 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801889
Synchronous semiconductor memory device Feb 17, 1997 Issued
Array ( [id] => 3826064 [patent_doc_number] => 05771188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Adjustable cell plate generator' [patent_app_type] => 1 [patent_app_number] => 8/800715 [patent_app_country] => US [patent_app_date] => 1997-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4135 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771188.pdf [firstpage_image] =>[orig_patent_app_number] => 800715 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/800715
Adjustable cell plate generator Feb 16, 1997 Issued
Array ( [id] => 3733336 [patent_doc_number] => 05701264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Dynamic random access memory cell having increased capacitance' [patent_app_type] => 1 [patent_app_number] => 8/792460 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701264.pdf [firstpage_image] =>[orig_patent_app_number] => 792460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792460
Dynamic random access memory cell having increased capacitance Jan 30, 1997 Issued
Array ( [id] => 4054462 [patent_doc_number] => 05912843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Scalable flash EEPROM memory cell, method of manufacturing and operation thereof' [patent_app_type] => 1 [patent_app_number] => 8/791863 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9361 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912843.pdf [firstpage_image] =>[orig_patent_app_number] => 791863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/791863
Scalable flash EEPROM memory cell, method of manufacturing and operation thereof Jan 30, 1997 Issued
Menu