Son Luu Mai

Array ( [id] => 3792567 [patent_doc_number] => 05818790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method for driving word lines in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/777224 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4858 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818790.pdf [firstpage_image] =>[orig_patent_app_number] => 777224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4061033 [patent_doc_number] => 05870330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method of making and structure of SRAM storage cell with N channel thin film transistor load devices' [patent_app_type] => 1 [patent_app_number] => 8/774911 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1933 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870330.pdf [firstpage_image] =>[orig_patent_app_number] => 774911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873230 [patent_doc_number] => 05796652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Non-volatile semiconductor memory capable of writing multi-value information' [patent_app_type] => 1 [patent_app_number] => 8/773834 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4985 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796652.pdf [firstpage_image] =>[orig_patent_app_number] => 773834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3756974 [patent_doc_number] => 05717650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Row/column decoder circuits for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/778720 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4785 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717650.pdf [firstpage_image] =>[orig_patent_app_number] => 778720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3854040 [patent_doc_number] => 05745427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Phase-shifted embedded ram apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/773706 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2051 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745427.pdf [firstpage_image] =>[orig_patent_app_number] => 773706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970959 [patent_doc_number] => 05901086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Pipelined fast-access floating gate memory architecture and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/780120 [patent_app_country] => US [patent_app_date] => 1996-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6296 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901086.pdf [firstpage_image] =>[orig_patent_app_number] => 780120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3854027 [patent_doc_number] => 05745426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Memory card and circuit board used therefor' [patent_app_type] => 1 [patent_app_number] => 8/773332 [patent_app_country] => US [patent_app_date] => 1996-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3639 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745426.pdf [firstpage_image] =>[orig_patent_app_number] => 773332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3789067 [patent_doc_number] => 05808932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Memory system which enables storage and retrieval of more than two states in a memory cell' [patent_app_type] => 1 [patent_app_number] => 8/779991 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4534 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808932.pdf [firstpage_image] =>[orig_patent_app_number] => 779991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3891801 [patent_doc_number] => 05798969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Data output buffer control circuit of a synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/770784 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2621 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798969.pdf [firstpage_image] =>[orig_patent_app_number] => 770784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3844660 [patent_doc_number] => 05761136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Circuit for generating a column switch enable signal of a memory' [patent_app_type] => 1 [patent_app_number] => 8/769990 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 4620 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761136.pdf [firstpage_image] =>[orig_patent_app_number] => 769990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4010607 [patent_doc_number] => 05923593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Multi-port DRAM cell and memory system using same' [patent_app_type] => 1 [patent_app_number] => 8/767707 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923593.pdf [firstpage_image] =>[orig_patent_app_number] => 767707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3822501 [patent_doc_number] => 05710738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Low power dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/768983 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2063 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710738.pdf [firstpage_image] =>[orig_patent_app_number] => 768983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873993 [patent_doc_number] => 05793694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Semiconductor integrated circuit device having means for peak current reduction' [patent_app_type] => 1 [patent_app_number] => 8/767724 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 4441 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793694.pdf [firstpage_image] =>[orig_patent_app_number] => 767724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3739368 [patent_doc_number] => 05703831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence' [patent_app_type] => 1 [patent_app_number] => 8/768081 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 9857 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703831.pdf [firstpage_image] =>[orig_patent_app_number] => 768081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892144 [patent_doc_number] => 05805505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Circuit and method for converting a pair of input signals into a level-limited output signal' [patent_app_type] => 1 [patent_app_number] => 8/767181 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7854 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805505.pdf [firstpage_image] =>[orig_patent_app_number] => 767181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3898937 [patent_doc_number] => 05724297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Semiconductor integrated circuit device and method of activating the same' [patent_app_type] => 1 [patent_app_number] => 8/762883 [patent_app_country] => US [patent_app_date] => 1996-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 20086 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724297.pdf [firstpage_image] =>[orig_patent_app_number] => 762883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3784068 [patent_doc_number] => 05774413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Sensed wordline driver' [patent_app_type] => 1 [patent_app_number] => 8/764329 [patent_app_country] => US [patent_app_date] => 1996-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2950 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774413.pdf [firstpage_image] =>[orig_patent_app_number] => 764329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3783806 [patent_doc_number] => 05774396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Flash memory with row redundancy' [patent_app_type] => 1 [patent_app_number] => 8/762707 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9384 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774396.pdf [firstpage_image] =>[orig_patent_app_number] => 762707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3756668 [patent_doc_number] => 05801989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method and apparatus for optimizing erase and program times for a non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 8/762495 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5446 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801989.pdf [firstpage_image] =>[orig_patent_app_number] => 762495 [rel_patent_id] =>[rel_patent_doc_number] =>)