
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3844700
[patent_doc_number] => 05761139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Semiconductor memory having redundancy memory cells'
[patent_app_type] => 1
[patent_app_number] => 8/761482
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 56
[patent_no_of_words] => 17613
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/761/05761139.pdf
[firstpage_image] =>[orig_patent_app_number] => 761482
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761482 | Semiconductor memory having redundancy memory cells | Dec 5, 1996 | Issued |
Array
(
[id] => 3808064
[patent_doc_number] => 05781498
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Sub word line driving circuit and a semiconductor memory device using the same'
[patent_app_type] => 1
[patent_app_number] => 8/764083
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2889
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/781/05781498.pdf
[firstpage_image] =>[orig_patent_app_number] => 764083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764083 | Sub word line driving circuit and a semiconductor memory device using the same | Dec 5, 1996 | Issued |
Array
(
[id] => 3913054
[patent_doc_number] => 05751646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Redundancy elements using thin film transistors (TFTS)'
[patent_app_type] => 1
[patent_app_number] => 8/761624
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1438
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751646.pdf
[firstpage_image] =>[orig_patent_app_number] => 761624
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761624 | Redundancy elements using thin film transistors (TFTS) | Dec 4, 1996 | Issued |
Array
(
[id] => 3789038
[patent_doc_number] => 05808929
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Nonvolatile content addressable memory'
[patent_app_type] => 1
[patent_app_number] => 8/761039
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 6398
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808929.pdf
[firstpage_image] =>[orig_patent_app_number] => 761039
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761039 | Nonvolatile content addressable memory | Dec 4, 1996 | Issued |
Array
(
[id] => 3889343
[patent_doc_number] => 05825687
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Low voltage memory cell, circuit array formed thereby and method of operation therefor'
[patent_app_type] => 1
[patent_app_number] => 8/760584
[patent_app_country] => US
[patent_app_date] => 1996-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 14728
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 334
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825687.pdf
[firstpage_image] =>[orig_patent_app_number] => 760584
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760584 | Low voltage memory cell, circuit array formed thereby and method of operation therefor | Dec 3, 1996 | Issued |
Array
(
[id] => 3819159
[patent_doc_number] => 05831772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Compact zoom lens'
[patent_app_type] => 1
[patent_app_number] => 8/763625
[patent_app_country] => US
[patent_app_date] => 1996-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 43
[patent_no_of_words] => 8409
[patent_no_of_claims] => 16
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[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/831/05831772.pdf
[firstpage_image] =>[orig_patent_app_number] => 763625
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763625 | Compact zoom lens | Dec 3, 1996 | Issued |
Array
(
[id] => 3698070
[patent_doc_number] => 05691946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Row redundancy block architecture'
[patent_app_type] => 1
[patent_app_number] => 8/758783
[patent_app_country] => US
[patent_app_date] => 1996-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 4356
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/691/05691946.pdf
[firstpage_image] =>[orig_patent_app_number] => 758783
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758783 | Row redundancy block architecture | Dec 2, 1996 | Issued |
Array
(
[id] => 3837826
[patent_doc_number] => 05784330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Evenly distributed RC delay word line decoding and mapping'
[patent_app_type] => 1
[patent_app_number] => 8/752981
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2870
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784330.pdf
[firstpage_image] =>[orig_patent_app_number] => 752981
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/752981 | Evenly distributed RC delay word line decoding and mapping | Dec 1, 1996 | Issued |
Array
(
[id] => 3830670
[patent_doc_number] => 05790466
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Multiple precharging semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/757928
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7187
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/790/05790466.pdf
[firstpage_image] =>[orig_patent_app_number] => 757928
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757928 | Multiple precharging semiconductor memory device | Nov 26, 1996 | Issued |
Array
(
[id] => 3892475
[patent_doc_number] => 05748541
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Latch circuit operating in synchronization with clock signals'
[patent_app_type] => 1
[patent_app_number] => 8/757728
[patent_app_country] => US
[patent_app_date] => 1996-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 11203
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748541.pdf
[firstpage_image] =>[orig_patent_app_number] => 757728
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757728 | Latch circuit operating in synchronization with clock signals | Nov 25, 1996 | Issued |
Array
(
[id] => 3802488
[patent_doc_number] => 05841707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Apparatus and method for a programmable interval timing generator in a semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 8/758138
[patent_app_country] => US
[patent_app_date] => 1996-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2898
[patent_no_of_claims] => 1
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[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841707.pdf
[firstpage_image] =>[orig_patent_app_number] => 758138
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758138 | Apparatus and method for a programmable interval timing generator in a semiconductor memory | Nov 24, 1996 | Issued |
Array
(
[id] => 3873865
[patent_doc_number] => 05793686
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output'
[patent_app_type] => 1
[patent_app_number] => 8/755930
[patent_app_country] => US
[patent_app_date] => 1996-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
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[patent_no_of_words] => 33166
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/793/05793686.pdf
[firstpage_image] =>[orig_patent_app_number] => 755930
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/755930 | Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output | Nov 24, 1996 | Issued |
Array
(
[id] => 3764879
[patent_doc_number] => 05721700
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Non-volatile semiconductor memory device in which applied voltage to ferroelectric capacitor is adjusted'
[patent_app_type] => 1
[patent_app_number] => 8/754533
[patent_app_country] => US
[patent_app_date] => 1996-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 10334
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721700.pdf
[firstpage_image] =>[orig_patent_app_number] => 754533
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754533 | Non-volatile semiconductor memory device in which applied voltage to ferroelectric capacitor is adjusted | Nov 20, 1996 | Issued |
Array
(
[id] => 3706707
[patent_doc_number] => 05677870
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-14
[patent_title] => 'Non-volatile programmable bistable multivibrator, programmable by the source, for the memory redundancy circuit'
[patent_app_type] => 1
[patent_app_number] => 8/752814
[patent_app_country] => US
[patent_app_date] => 1996-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3354
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 126
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/677/05677870.pdf
[firstpage_image] =>[orig_patent_app_number] => 752814
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/752814 | Non-volatile programmable bistable multivibrator, programmable by the source, for the memory redundancy circuit | Nov 20, 1996 | Issued |
Array
(
[id] => 3764961
[patent_doc_number] => 05721706
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Non-volatile-programmable bistable multivibrator, programmable by the source, for memory redundancy circuit'
[patent_app_type] => 1
[patent_app_number] => 8/754432
[patent_app_country] => US
[patent_app_date] => 1996-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721706.pdf
[firstpage_image] =>[orig_patent_app_number] => 754432
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754432 | Non-volatile-programmable bistable multivibrator, programmable by the source, for memory redundancy circuit | Nov 20, 1996 | Issued |
Array
(
[id] => 3892297
[patent_doc_number] => 05748529
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Integrated circuit memory devices having direct read capability'
[patent_app_type] => 1
[patent_app_number] => 8/749332
[patent_app_country] => US
[patent_app_date] => 1996-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3066
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748529.pdf
[firstpage_image] =>[orig_patent_app_number] => 749332
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749332 | Integrated circuit memory devices having direct read capability | Nov 13, 1996 | Issued |
Array
(
[id] => 3866896
[patent_doc_number] => 05768193
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Bit-refreshable method and circuit for refreshing a nonvolatile flash memory'
[patent_app_type] => 1
[patent_app_number] => 8/745034
[patent_app_country] => US
[patent_app_date] => 1996-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 8729
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/768/05768193.pdf
[firstpage_image] =>[orig_patent_app_number] => 745034
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/745034 | Bit-refreshable method and circuit for refreshing a nonvolatile flash memory | Nov 6, 1996 | Issued |
Array
(
[id] => 3892188
[patent_doc_number] => 05748521
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Metal plug capacitor structures for integrated circuit devices and related methods'
[patent_app_type] => 1
[patent_app_number] => 8/746129
[patent_app_country] => US
[patent_app_date] => 1996-11-06
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748521.pdf
[firstpage_image] =>[orig_patent_app_number] => 746129
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/746129 | Metal plug capacitor structures for integrated circuit devices and related methods | Nov 5, 1996 | Issued |
Array
(
[id] => 3892791
[patent_doc_number] => 05748561
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Semiconductor memory device with fast successive read operation'
[patent_app_type] => 1
[patent_app_number] => 8/742338
[patent_app_country] => US
[patent_app_date] => 1996-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748561.pdf
[firstpage_image] =>[orig_patent_app_number] => 742338
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/742338 | Semiconductor memory device with fast successive read operation | Oct 31, 1996 | Issued |
Array
(
[id] => 3891919
[patent_doc_number] => 05798977
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Power line coupling prevention circuit for semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/742681
[patent_app_country] => US
[patent_app_date] => 1996-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1448
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[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/798/05798977.pdf
[firstpage_image] =>[orig_patent_app_number] => 742681
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/742681 | Power line coupling prevention circuit for semiconductor memory device | Oct 30, 1996 | Issued |