
Son Luu Mai
Examiner (ID: 18155)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818 |
| Total Applications | 3063 |
| Issued Applications | 2917 |
| Pending Applications | 45 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3822501
[patent_doc_number] => 05710738
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-20
[patent_title] => 'Low power dynamic random access memory'
[patent_app_type] => 1
[patent_app_number] => 8/768983
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2063
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/710/05710738.pdf
[firstpage_image] =>[orig_patent_app_number] => 768983
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768983 | Low power dynamic random access memory | Dec 16, 1996 | Issued |
Array
(
[id] => 3739368
[patent_doc_number] => 05703831
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence'
[patent_app_type] => 1
[patent_app_number] => 8/768081
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 9857
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/703/05703831.pdf
[firstpage_image] =>[orig_patent_app_number] => 768081
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768081 | Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence | Dec 15, 1996 | Issued |
Array
(
[id] => 3892144
[patent_doc_number] => 05805505
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Circuit and method for converting a pair of input signals into a level-limited output signal'
[patent_app_type] => 1
[patent_app_number] => 8/767181
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7854
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805505.pdf
[firstpage_image] =>[orig_patent_app_number] => 767181
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767181 | Circuit and method for converting a pair of input signals into a level-limited output signal | Dec 15, 1996 | Issued |
Array
(
[id] => 3898937
[patent_doc_number] => 05724297
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Semiconductor integrated circuit device and method of activating the same'
[patent_app_type] => 1
[patent_app_number] => 8/762883
[patent_app_country] => US
[patent_app_date] => 1996-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 23
[patent_no_of_words] => 20086
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/724/05724297.pdf
[firstpage_image] =>[orig_patent_app_number] => 762883
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762883 | Semiconductor integrated circuit device and method of activating the same | Dec 11, 1996 | Issued |
Array
(
[id] => 3784068
[patent_doc_number] => 05774413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Sensed wordline driver'
[patent_app_type] => 1
[patent_app_number] => 8/764329
[patent_app_country] => US
[patent_app_date] => 1996-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2950
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774413.pdf
[firstpage_image] =>[orig_patent_app_number] => 764329
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764329 | Sensed wordline driver | Dec 11, 1996 | Issued |
| 08/764665 | METHOD AND CIRCUITRY FOR STORING DISCRETE AMOUNTS OF CHARGE IN A SINGLE MEMORY ELEMENT | Dec 10, 1996 | Abandoned |
Array
(
[id] => 3783806
[patent_doc_number] => 05774396
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Flash memory with row redundancy'
[patent_app_type] => 1
[patent_app_number] => 8/762707
[patent_app_country] => US
[patent_app_date] => 1996-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9384
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774396.pdf
[firstpage_image] =>[orig_patent_app_number] => 762707
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762707 | Flash memory with row redundancy | Dec 8, 1996 | Issued |
Array
(
[id] => 3756668
[patent_doc_number] => 05801989
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Method and apparatus for optimizing erase and program times for a non-volatile memory device'
[patent_app_type] => 1
[patent_app_number] => 8/762495
[patent_app_country] => US
[patent_app_date] => 1996-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 5446
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/801/05801989.pdf
[firstpage_image] =>[orig_patent_app_number] => 762495
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762495 | Method and apparatus for optimizing erase and program times for a non-volatile memory device | Dec 8, 1996 | Issued |
Array
(
[id] => 3808064
[patent_doc_number] => 05781498
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Sub word line driving circuit and a semiconductor memory device using the same'
[patent_app_type] => 1
[patent_app_number] => 8/764083
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2889
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/781/05781498.pdf
[firstpage_image] =>[orig_patent_app_number] => 764083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764083 | Sub word line driving circuit and a semiconductor memory device using the same | Dec 5, 1996 | Issued |
Array
(
[id] => 3844700
[patent_doc_number] => 05761139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Semiconductor memory having redundancy memory cells'
[patent_app_type] => 1
[patent_app_number] => 8/761482
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 56
[patent_no_of_words] => 17613
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/761/05761139.pdf
[firstpage_image] =>[orig_patent_app_number] => 761482
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761482 | Semiconductor memory having redundancy memory cells | Dec 5, 1996 | Issued |
Array
(
[id] => 3789038
[patent_doc_number] => 05808929
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Nonvolatile content addressable memory'
[patent_app_type] => 1
[patent_app_number] => 8/761039
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 6398
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808929.pdf
[firstpage_image] =>[orig_patent_app_number] => 761039
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761039 | Nonvolatile content addressable memory | Dec 4, 1996 | Issued |
Array
(
[id] => 3913054
[patent_doc_number] => 05751646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Redundancy elements using thin film transistors (TFTS)'
[patent_app_type] => 1
[patent_app_number] => 8/761624
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1438
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751646.pdf
[firstpage_image] =>[orig_patent_app_number] => 761624
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761624 | Redundancy elements using thin film transistors (TFTS) | Dec 4, 1996 | Issued |
Array
(
[id] => 3889343
[patent_doc_number] => 05825687
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Low voltage memory cell, circuit array formed thereby and method of operation therefor'
[patent_app_type] => 1
[patent_app_number] => 8/760584
[patent_app_country] => US
[patent_app_date] => 1996-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 14728
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 334
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825687.pdf
[firstpage_image] =>[orig_patent_app_number] => 760584
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760584 | Low voltage memory cell, circuit array formed thereby and method of operation therefor | Dec 3, 1996 | Issued |
Array
(
[id] => 3819159
[patent_doc_number] => 05831772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Compact zoom lens'
[patent_app_type] => 1
[patent_app_number] => 8/763625
[patent_app_country] => US
[patent_app_date] => 1996-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 43
[patent_no_of_words] => 8409
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/831/05831772.pdf
[firstpage_image] =>[orig_patent_app_number] => 763625
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763625 | Compact zoom lens | Dec 3, 1996 | Issued |
Array
(
[id] => 3698070
[patent_doc_number] => 05691946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Row redundancy block architecture'
[patent_app_type] => 1
[patent_app_number] => 8/758783
[patent_app_country] => US
[patent_app_date] => 1996-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 4356
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/691/05691946.pdf
[firstpage_image] =>[orig_patent_app_number] => 758783
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758783 | Row redundancy block architecture | Dec 2, 1996 | Issued |
Array
(
[id] => 3837826
[patent_doc_number] => 05784330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Evenly distributed RC delay word line decoding and mapping'
[patent_app_type] => 1
[patent_app_number] => 8/752981
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2870
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784330.pdf
[firstpage_image] =>[orig_patent_app_number] => 752981
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/752981 | Evenly distributed RC delay word line decoding and mapping | Dec 1, 1996 | Issued |
Array
(
[id] => 3830670
[patent_doc_number] => 05790466
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Multiple precharging semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/757928
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 7187
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/790/05790466.pdf
[firstpage_image] =>[orig_patent_app_number] => 757928
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757928 | Multiple precharging semiconductor memory device | Nov 26, 1996 | Issued |
Array
(
[id] => 3892475
[patent_doc_number] => 05748541
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Latch circuit operating in synchronization with clock signals'
[patent_app_type] => 1
[patent_app_number] => 8/757728
[patent_app_country] => US
[patent_app_date] => 1996-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 11203
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748541.pdf
[firstpage_image] =>[orig_patent_app_number] => 757728
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757728 | Latch circuit operating in synchronization with clock signals | Nov 25, 1996 | Issued |
Array
(
[id] => 3873865
[patent_doc_number] => 05793686
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output'
[patent_app_type] => 1
[patent_app_number] => 8/755930
[patent_app_country] => US
[patent_app_date] => 1996-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 56
[patent_no_of_words] => 33166
[patent_no_of_claims] => 11
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[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/793/05793686.pdf
[firstpage_image] =>[orig_patent_app_number] => 755930
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/755930 | Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output | Nov 24, 1996 | Issued |
Array
(
[id] => 3802488
[patent_doc_number] => 05841707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Apparatus and method for a programmable interval timing generator in a semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 8/758138
[patent_app_country] => US
[patent_app_date] => 1996-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2898
[patent_no_of_claims] => 1
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841707.pdf
[firstpage_image] =>[orig_patent_app_number] => 758138
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758138 | Apparatus and method for a programmable interval timing generator in a semiconductor memory | Nov 24, 1996 | Issued |