Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3844453 [patent_doc_number] => 05761120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Floating gate FPGA cell with select device on drain' [patent_app_type] => 1 [patent_app_number] => 8/703683 [patent_app_country] => US [patent_app_date] => 1996-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 5283 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761120.pdf [firstpage_image] =>[orig_patent_app_number] => 703683 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703683
Floating gate FPGA cell with select device on drain Aug 26, 1996 Issued
Array ( [id] => 3900814 [patent_doc_number] => 05777931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Synchronized redundancy decoding systems and methods for integrated circuit memory devices' [patent_app_type] => 1 [patent_app_number] => 8/703204 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3908 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777931.pdf [firstpage_image] =>[orig_patent_app_number] => 703204 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703204
Synchronized redundancy decoding systems and methods for integrated circuit memory devices Aug 25, 1996 Issued
Array ( [id] => 3697934 [patent_doc_number] => 05691937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Structure of split gate transistor for use in a non-volatile semiconductor memory and method of manufacturing such a split gate transistor' [patent_app_type] => 1 [patent_app_number] => 8/701013 [patent_app_country] => US [patent_app_date] => 1996-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 7487 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691937.pdf [firstpage_image] =>[orig_patent_app_number] => 701013 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701013
Structure of split gate transistor for use in a non-volatile semiconductor memory and method of manufacturing such a split gate transistor Aug 20, 1996 Issued
Array ( [id] => 3892253 [patent_doc_number] => 05748526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Circuit for repair of flash memory cells and a method of repair' [patent_app_type] => 1 [patent_app_number] => 8/698514 [patent_app_country] => US [patent_app_date] => 1996-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1828 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748526.pdf [firstpage_image] =>[orig_patent_app_number] => 698514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/698514
Circuit for repair of flash memory cells and a method of repair Aug 14, 1996 Issued
Array ( [id] => 3697920 [patent_doc_number] => 05691936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Magnetoresistive element and memory element' [patent_app_type] => 1 [patent_app_number] => 8/702382 [patent_app_country] => US [patent_app_date] => 1996-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5147 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691936.pdf [firstpage_image] =>[orig_patent_app_number] => 702382 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/702382
Magnetoresistive element and memory element Aug 13, 1996 Issued
Array ( [id] => 3874007 [patent_doc_number] => 05793695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Semiconductor memory device having level-shifted precharge signal' [patent_app_type] => 1 [patent_app_number] => 8/696738 [patent_app_country] => US [patent_app_date] => 1996-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 12351 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793695.pdf [firstpage_image] =>[orig_patent_app_number] => 696738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/696738
Semiconductor memory device having level-shifted precharge signal Aug 13, 1996 Issued
Array ( [id] => 3790048 [patent_doc_number] => 05757701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Semiconductor memory device having serial access port' [patent_app_type] => 1 [patent_app_number] => 8/691013 [patent_app_country] => US [patent_app_date] => 1996-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 2569 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757701.pdf [firstpage_image] =>[orig_patent_app_number] => 691013 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691013
Semiconductor memory device having serial access port Aug 4, 1996 Issued
Array ( [id] => 3825015 [patent_doc_number] => 05812465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Redundancy circuit and method for providing word lines driven by a shift register' [patent_app_type] => 1 [patent_app_number] => 8/691357 [patent_app_country] => US [patent_app_date] => 1996-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2999 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812465.pdf [firstpage_image] =>[orig_patent_app_number] => 691357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691357
Redundancy circuit and method for providing word lines driven by a shift register Aug 1, 1996 Issued
Array ( [id] => 3845400 [patent_doc_number] => 05815430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Circuit and method for reducing compensation of a ferroelectric capacitor by multiple pulsing of the plate line following a write operation' [patent_app_type] => 1 [patent_app_number] => 8/691132 [patent_app_country] => US [patent_app_date] => 1996-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7011 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815430.pdf [firstpage_image] =>[orig_patent_app_number] => 691132 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691132
Circuit and method for reducing compensation of a ferroelectric capacitor by multiple pulsing of the plate line following a write operation Jul 31, 1996 Issued
Array ( [id] => 3706723 [patent_doc_number] => 05677871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Circuit structure for a memory matrix and corresponding manufacturing method' [patent_app_type] => 1 [patent_app_number] => 8/688233 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3676 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677871.pdf [firstpage_image] =>[orig_patent_app_number] => 688233 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/688233
Circuit structure for a memory matrix and corresponding manufacturing method Jul 28, 1996 Issued
Array ( [id] => 3780921 [patent_doc_number] => 05734618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Memory card with low power consumption in inactive state' [patent_app_type] => 1 [patent_app_number] => 8/690318 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4116 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734618.pdf [firstpage_image] =>[orig_patent_app_number] => 690318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/690318
Memory card with low power consumption in inactive state Jul 24, 1996 Issued
Array ( [id] => 3752001 [patent_doc_number] => 05787033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Semiconductor memory device with reduced probability of power consumption' [patent_app_type] => 1 [patent_app_number] => 8/684209 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 36 [patent_no_of_words] => 22356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787033.pdf [firstpage_image] =>[orig_patent_app_number] => 684209 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684209
Semiconductor memory device with reduced probability of power consumption Jul 18, 1996 Issued
Array ( [id] => 3756739 [patent_doc_number] => 05717634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Programmable and convertible non-volatile memory array' [patent_app_type] => 1 [patent_app_number] => 8/684650 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 7122 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717634.pdf [firstpage_image] =>[orig_patent_app_number] => 684650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684650
Programmable and convertible non-volatile memory array Jul 18, 1996 Issued
Array ( [id] => 3897679 [patent_doc_number] => 05715196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Method for driving a non-volatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/684178 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 68 [patent_no_of_words] => 19633 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715196.pdf [firstpage_image] =>[orig_patent_app_number] => 684178 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684178
Method for driving a non-volatile semiconductor memory Jul 18, 1996 Issued
Array ( [id] => 3764990 [patent_doc_number] => 05721708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Reduction of the address pins of the integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/679883 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1899 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721708.pdf [firstpage_image] =>[orig_patent_app_number] => 679883 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679883
Reduction of the address pins of the integrated circuit Jul 14, 1996 Issued
Array ( [id] => 3798580 [patent_doc_number] => 05737270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Precharged wordline decoder with locally-controlled clock' [patent_app_type] => 1 [patent_app_number] => 8/680081 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2805 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737270.pdf [firstpage_image] =>[orig_patent_app_number] => 680081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/680081
Precharged wordline decoder with locally-controlled clock Jul 14, 1996 Issued
Array ( [id] => 3756627 [patent_doc_number] => 05801986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Semiconductor memory device having both redundancy and test capability and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/679712 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7961 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801986.pdf [firstpage_image] =>[orig_patent_app_number] => 679712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679712
Semiconductor memory device having both redundancy and test capability and method of manufacturing the same Jul 11, 1996 Issued
Array ( [id] => 3706737 [patent_doc_number] => 05677872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors' [patent_app_type] => 1 [patent_app_number] => 8/676422 [patent_app_country] => US [patent_app_date] => 1996-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4585 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677872.pdf [firstpage_image] =>[orig_patent_app_number] => 676422 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/676422
Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors Jul 7, 1996 Issued
Array ( [id] => 3741847 [patent_doc_number] => 05694352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Semiconductor memory device having layout area of periphery of output pad reduced' [patent_app_type] => 1 [patent_app_number] => 8/676705 [patent_app_country] => US [patent_app_date] => 1996-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4499 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694352.pdf [firstpage_image] =>[orig_patent_app_number] => 676705 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/676705
Semiconductor memory device having layout area of periphery of output pad reduced Jul 7, 1996 Issued
Array ( [id] => 3807954 [patent_doc_number] => 05781490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Multiple staged power up of integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/675007 [patent_app_country] => US [patent_app_date] => 1996-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4731 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781490.pdf [firstpage_image] =>[orig_patent_app_number] => 675007 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/675007
Multiple staged power up of integrated circuit Jul 2, 1996 Issued
Menu