
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3845400
[patent_doc_number] => 05815430
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Circuit and method for reducing compensation of a ferroelectric capacitor by multiple pulsing of the plate line following a write operation'
[patent_app_type] => 1
[patent_app_number] => 8/691132
[patent_app_country] => US
[patent_app_date] => 1996-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7011
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/815/05815430.pdf
[firstpage_image] =>[orig_patent_app_number] => 691132
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/691132 | Circuit and method for reducing compensation of a ferroelectric capacitor by multiple pulsing of the plate line following a write operation | Jul 31, 1996 | Issued |
Array
(
[id] => 3706723
[patent_doc_number] => 05677871
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-14
[patent_title] => 'Circuit structure for a memory matrix and corresponding manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 8/688233
[patent_app_country] => US
[patent_app_date] => 1996-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3676
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/677/05677871.pdf
[firstpage_image] =>[orig_patent_app_number] => 688233
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/688233 | Circuit structure for a memory matrix and corresponding manufacturing method | Jul 28, 1996 | Issued |
Array
(
[id] => 3780921
[patent_doc_number] => 05734618
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-31
[patent_title] => 'Memory card with low power consumption in inactive state'
[patent_app_type] => 1
[patent_app_number] => 8/690318
[patent_app_country] => US
[patent_app_date] => 1996-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 4116
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/734/05734618.pdf
[firstpage_image] =>[orig_patent_app_number] => 690318
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/690318 | Memory card with low power consumption in inactive state | Jul 24, 1996 | Issued |
Array
(
[id] => 3897679
[patent_doc_number] => 05715196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Method for driving a non-volatile semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 8/684178
[patent_app_country] => US
[patent_app_date] => 1996-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 68
[patent_no_of_words] => 19633
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/715/05715196.pdf
[firstpage_image] =>[orig_patent_app_number] => 684178
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/684178 | Method for driving a non-volatile semiconductor memory | Jul 18, 1996 | Issued |
Array
(
[id] => 3752001
[patent_doc_number] => 05787033
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Semiconductor memory device with reduced probability of power consumption'
[patent_app_type] => 1
[patent_app_number] => 8/684209
[patent_app_country] => US
[patent_app_date] => 1996-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 36
[patent_no_of_words] => 22356
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/787/05787033.pdf
[firstpage_image] =>[orig_patent_app_number] => 684209
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/684209 | Semiconductor memory device with reduced probability of power consumption | Jul 18, 1996 | Issued |
Array
(
[id] => 3756739
[patent_doc_number] => 05717634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Programmable and convertible non-volatile memory array'
[patent_app_type] => 1
[patent_app_number] => 8/684650
[patent_app_country] => US
[patent_app_date] => 1996-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 7122
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 350
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717634.pdf
[firstpage_image] =>[orig_patent_app_number] => 684650
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/684650 | Programmable and convertible non-volatile memory array | Jul 18, 1996 | Issued |
Array
(
[id] => 3764990
[patent_doc_number] => 05721708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Reduction of the address pins of the integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/679883
[patent_app_country] => US
[patent_app_date] => 1996-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1899
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721708.pdf
[firstpage_image] =>[orig_patent_app_number] => 679883
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/679883 | Reduction of the address pins of the integrated circuit | Jul 14, 1996 | Issued |
Array
(
[id] => 3798580
[patent_doc_number] => 05737270
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Precharged wordline decoder with locally-controlled clock'
[patent_app_type] => 1
[patent_app_number] => 8/680081
[patent_app_country] => US
[patent_app_date] => 1996-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2805
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/737/05737270.pdf
[firstpage_image] =>[orig_patent_app_number] => 680081
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/680081 | Precharged wordline decoder with locally-controlled clock | Jul 14, 1996 | Issued |
Array
(
[id] => 3756627
[patent_doc_number] => 05801986
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Semiconductor memory device having both redundancy and test capability and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/679712
[patent_app_country] => US
[patent_app_date] => 1996-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 7961
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/801/05801986.pdf
[firstpage_image] =>[orig_patent_app_number] => 679712
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/679712 | Semiconductor memory device having both redundancy and test capability and method of manufacturing the same | Jul 11, 1996 | Issued |
Array
(
[id] => 3741847
[patent_doc_number] => 05694352
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Semiconductor memory device having layout area of periphery of output pad reduced'
[patent_app_type] => 1
[patent_app_number] => 8/676705
[patent_app_country] => US
[patent_app_date] => 1996-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4499
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/694/05694352.pdf
[firstpage_image] =>[orig_patent_app_number] => 676705
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/676705 | Semiconductor memory device having layout area of periphery of output pad reduced | Jul 7, 1996 | Issued |
Array
(
[id] => 3706737
[patent_doc_number] => 05677872
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-14
[patent_title] => 'Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors'
[patent_app_type] => 1
[patent_app_number] => 8/676422
[patent_app_country] => US
[patent_app_date] => 1996-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 4585
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/677/05677872.pdf
[firstpage_image] =>[orig_patent_app_number] => 676422
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/676422 | Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors | Jul 7, 1996 | Issued |
Array
(
[id] => 3807954
[patent_doc_number] => 05781490
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Multiple staged power up of integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/675007
[patent_app_country] => US
[patent_app_date] => 1996-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4731
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/781/05781490.pdf
[firstpage_image] =>[orig_patent_app_number] => 675007
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/675007 | Multiple staged power up of integrated circuit | Jul 2, 1996 | Issued |
Array
(
[id] => 3697887
[patent_doc_number] => 05663914
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Mode adaptive data output buffer for semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/673211
[patent_app_country] => US
[patent_app_date] => 1996-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2454
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/663/05663914.pdf
[firstpage_image] =>[orig_patent_app_number] => 673211
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/673211 | Mode adaptive data output buffer for semiconductor memory device | Jun 26, 1996 | Issued |
| 08/669668 | REFERENCE POTENTIAL GENERATOR AND A SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME | Jun 23, 1996 | Abandoned |
Array
(
[id] => 3746958
[patent_doc_number] => 05754066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Output stage for buffering an electrical signal and method for performing the same'
[patent_app_type] => 1
[patent_app_number] => 8/665370
[patent_app_country] => US
[patent_app_date] => 1996-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6867
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754066.pdf
[firstpage_image] =>[orig_patent_app_number] => 665370
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665370 | Output stage for buffering an electrical signal and method for performing the same | Jun 18, 1996 | Issued |
Array
(
[id] => 3659064
[patent_doc_number] => 05684736
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Multilevel memory cell sense amplifier system'
[patent_app_type] => 1
[patent_app_number] => 8/664601
[patent_app_country] => US
[patent_app_date] => 1996-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 6291
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/684/05684736.pdf
[firstpage_image] =>[orig_patent_app_number] => 664601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/664601 | Multilevel memory cell sense amplifier system | Jun 16, 1996 | Issued |
Array
(
[id] => 3697742
[patent_doc_number] => 05663904
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Ferroelectric memory using pair of reference cells'
[patent_app_type] => 1
[patent_app_number] => 8/661782
[patent_app_country] => US
[patent_app_date] => 1996-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 6845
[patent_no_of_claims] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/663/05663904.pdf
[firstpage_image] =>[orig_patent_app_number] => 661782
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/661782 | Ferroelectric memory using pair of reference cells | Jun 12, 1996 | Issued |
Array
(
[id] => 3888866
[patent_doc_number] => 05764585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Semiconductor memory device having main word lines and sub word lines'
[patent_app_type] => 1
[patent_app_number] => 8/660281
[patent_app_country] => US
[patent_app_date] => 1996-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2649
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764585.pdf
[firstpage_image] =>[orig_patent_app_number] => 660281
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/660281 | Semiconductor memory device having main word lines and sub word lines | Jun 6, 1996 | Issued |
Array
(
[id] => 3674323
[patent_doc_number] => 05668765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'Charge transfer sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/659384
[patent_app_country] => US
[patent_app_date] => 1996-06-06
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/668/05668765.pdf
[firstpage_image] =>[orig_patent_app_number] => 659384
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/659384 | Charge transfer sense amplifier | Jun 5, 1996 | Issued |
Array
(
[id] => 3672422
[patent_doc_number] => 05625592
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit'
[patent_app_type] => 1
[patent_app_number] => 8/657484
[patent_app_country] => US
[patent_app_date] => 1996-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 14640
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/625/05625592.pdf
[firstpage_image] =>[orig_patent_app_number] => 657484
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/657484 | Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit | May 22, 1996 | Issued |