
Son Luu Mai
Examiner (ID: 18155)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818 |
| Total Applications | 3063 |
| Issued Applications | 2917 |
| Pending Applications | 45 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3697887
[patent_doc_number] => 05663914
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Mode adaptive data output buffer for semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/673211
[patent_app_country] => US
[patent_app_date] => 1996-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2454
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/663/05663914.pdf
[firstpage_image] =>[orig_patent_app_number] => 673211
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/673211 | Mode adaptive data output buffer for semiconductor memory device | Jun 26, 1996 | Issued |
| 08/669668 | REFERENCE POTENTIAL GENERATOR AND A SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME | Jun 23, 1996 | Abandoned |
Array
(
[id] => 3746958
[patent_doc_number] => 05754066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Output stage for buffering an electrical signal and method for performing the same'
[patent_app_type] => 1
[patent_app_number] => 8/665370
[patent_app_country] => US
[patent_app_date] => 1996-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6867
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754066.pdf
[firstpage_image] =>[orig_patent_app_number] => 665370
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665370 | Output stage for buffering an electrical signal and method for performing the same | Jun 18, 1996 | Issued |
Array
(
[id] => 3659064
[patent_doc_number] => 05684736
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Multilevel memory cell sense amplifier system'
[patent_app_type] => 1
[patent_app_number] => 8/664601
[patent_app_country] => US
[patent_app_date] => 1996-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6291
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/684/05684736.pdf
[firstpage_image] =>[orig_patent_app_number] => 664601
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/664601 | Multilevel memory cell sense amplifier system | Jun 16, 1996 | Issued |
Array
(
[id] => 3697742
[patent_doc_number] => 05663904
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Ferroelectric memory using pair of reference cells'
[patent_app_type] => 1
[patent_app_number] => 8/661782
[patent_app_country] => US
[patent_app_date] => 1996-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 34
[patent_no_of_words] => 6845
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/663/05663904.pdf
[firstpage_image] =>[orig_patent_app_number] => 661782
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/661782 | Ferroelectric memory using pair of reference cells | Jun 12, 1996 | Issued |
Array
(
[id] => 3888866
[patent_doc_number] => 05764585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Semiconductor memory device having main word lines and sub word lines'
[patent_app_type] => 1
[patent_app_number] => 8/660281
[patent_app_country] => US
[patent_app_date] => 1996-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2649
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764585.pdf
[firstpage_image] =>[orig_patent_app_number] => 660281
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/660281 | Semiconductor memory device having main word lines and sub word lines | Jun 6, 1996 | Issued |
Array
(
[id] => 3674323
[patent_doc_number] => 05668765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'Charge transfer sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/659384
[patent_app_country] => US
[patent_app_date] => 1996-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2530
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/668/05668765.pdf
[firstpage_image] =>[orig_patent_app_number] => 659384
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/659384 | Charge transfer sense amplifier | Jun 5, 1996 | Issued |
Array
(
[id] => 3672422
[patent_doc_number] => 05625592
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit'
[patent_app_type] => 1
[patent_app_number] => 8/657484
[patent_app_country] => US
[patent_app_date] => 1996-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 25
[patent_no_of_words] => 14640
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/625/05625592.pdf
[firstpage_image] =>[orig_patent_app_number] => 657484
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/657484 | Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit | May 22, 1996 | Issued |
Array
(
[id] => 3747260
[patent_doc_number] => 05699295
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Current detection circuit for reading a memory in integrated circuit form'
[patent_app_type] => 1
[patent_app_number] => 8/649282
[patent_app_country] => US
[patent_app_date] => 1996-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2136
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/699/05699295.pdf
[firstpage_image] =>[orig_patent_app_number] => 649282
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/649282 | Current detection circuit for reading a memory in integrated circuit form | May 16, 1996 | Issued |
Array
(
[id] => 3841339
[patent_doc_number] => 05712817
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Highly integrated cell having a reading transistor and a writing transistor'
[patent_app_type] => 1
[patent_app_number] => 8/648755
[patent_app_country] => US
[patent_app_date] => 1996-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 4076
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/712/05712817.pdf
[firstpage_image] =>[orig_patent_app_number] => 648755
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/648755 | Highly integrated cell having a reading transistor and a writing transistor | May 15, 1996 | Issued |
Array
(
[id] => 3782588
[patent_doc_number] => 05757214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'PWM driver for an inductive load with detector of a not regulating PWM condition'
[patent_app_type] => 1
[patent_app_number] => 8/647851
[patent_app_country] => US
[patent_app_date] => 1996-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 77
[patent_no_of_words] => 8932
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/757/05757214.pdf
[firstpage_image] =>[orig_patent_app_number] => 647851
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/647851 | PWM driver for an inductive load with detector of a not regulating PWM condition | May 14, 1996 | Issued |
Array
(
[id] => 3703640
[patent_doc_number] => 05661677
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Circuit and method for on-board programming of PRD Serial EEPROMS'
[patent_app_type] => 1
[patent_app_number] => 8/648555
[patent_app_country] => US
[patent_app_date] => 1996-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2781
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/661/05661677.pdf
[firstpage_image] =>[orig_patent_app_number] => 648555
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/648555 | Circuit and method for on-board programming of PRD Serial EEPROMS | May 14, 1996 | Issued |
Array
(
[id] => 3733125
[patent_doc_number] => 05673227
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-30
[patent_title] => 'Integrated circuit memory with multiplexed redundant column data path'
[patent_app_type] => 1
[patent_app_number] => 8/645856
[patent_app_country] => US
[patent_app_date] => 1996-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3551
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/673/05673227.pdf
[firstpage_image] =>[orig_patent_app_number] => 645856
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/645856 | Integrated circuit memory with multiplexed redundant column data path | May 13, 1996 | Issued |
Array
(
[id] => 3638805
[patent_doc_number] => 05687119
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Semiconductor memory device with floating gate electrode'
[patent_app_type] => 1
[patent_app_number] => 8/646152
[patent_app_country] => US
[patent_app_date] => 1996-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 50
[patent_no_of_words] => 6430
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/687/05687119.pdf
[firstpage_image] =>[orig_patent_app_number] => 646152
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/646152 | Semiconductor memory device with floating gate electrode | May 6, 1996 | Issued |
Array
(
[id] => 3892283
[patent_doc_number] => 05748528
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'EEPROM memory device with simultaneous read and write sector capabilities'
[patent_app_type] => 1
[patent_app_number] => 8/642813
[patent_app_country] => US
[patent_app_date] => 1996-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 5665
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748528.pdf
[firstpage_image] =>[orig_patent_app_number] => 642813
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/642813 | EEPROM memory device with simultaneous read and write sector capabilities | May 2, 1996 | Issued |
Array
(
[id] => 3742043
[patent_doc_number] => 05694366
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'OP amp circuit with variable resistance and memory system including same'
[patent_app_type] => 1
[patent_app_number] => 8/640456
[patent_app_country] => US
[patent_app_date] => 1996-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 13625
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/694/05694366.pdf
[firstpage_image] =>[orig_patent_app_number] => 640456
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/640456 | OP amp circuit with variable resistance and memory system including same | Apr 30, 1996 | Issued |
Array
(
[id] => 3858465
[patent_doc_number] => 05719818
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-17
[patent_title] => 'Row decoder having triple transistor word line drivers'
[patent_app_type] => 1
[patent_app_number] => 8/634282
[patent_app_country] => US
[patent_app_date] => 1996-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 5746
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/719/05719818.pdf
[firstpage_image] =>[orig_patent_app_number] => 634282
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/634282 | Row decoder having triple transistor word line drivers | Apr 17, 1996 | Issued |
Array
(
[id] => 4027363
[patent_doc_number] => 05881012
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/633684
[patent_app_country] => US
[patent_app_date] => 1996-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9379
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/881/05881012.pdf
[firstpage_image] =>[orig_patent_app_number] => 633684
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/633684 | Semiconductor integrated circuit | Apr 16, 1996 | Issued |
Array
(
[id] => 3704433
[patent_doc_number] => 05680363
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-21
[patent_title] => 'Semiconductor memory capable of transferring data at a high speed between an SRAM and a DRAM array'
[patent_app_type] => 1
[patent_app_number] => 8/632279
[patent_app_country] => US
[patent_app_date] => 1996-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 43
[patent_no_of_words] => 24515
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/680/05680363.pdf
[firstpage_image] =>[orig_patent_app_number] => 632279
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/632279 | Semiconductor memory capable of transferring data at a high speed between an SRAM and a DRAM array | Apr 14, 1996 | Issued |
Array
(
[id] => 3638635
[patent_doc_number] => 05687108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Power bussing layout for memory circuits'
[patent_app_type] => 1
[patent_app_number] => 8/630283
[patent_app_country] => US
[patent_app_date] => 1996-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1866
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/687/05687108.pdf
[firstpage_image] =>[orig_patent_app_number] => 630283
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/630283 | Power bussing layout for memory circuits | Apr 9, 1996 | Issued |