Search

Son Luu Mai

Examiner (ID: 16593, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16417608 [patent_doc_number] => 10825508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-03 [patent_title] => Bit line structure for two-transistor static random access memory [patent_app_type] => utility [patent_app_number] => 16/712878 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2538 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712878 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/712878
Bit line structure for two-transistor static random access memory Dec 11, 2019 Issued
Array ( [id] => 16845750 [patent_doc_number] => 11017844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/712456 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8325 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712456 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/712456
Semiconductor memory device Dec 11, 2019 Issued
Array ( [id] => 16803098 [patent_doc_number] => 10998049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => Method of programming memory device and related memory device [patent_app_type] => utility [patent_app_number] => 16/705152 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3523 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705152
Method of programming memory device and related memory device Dec 4, 2019 Issued
Array ( [id] => 16881245 [patent_doc_number] => 11031402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-08 [patent_title] => Capacitorless dram cell [patent_app_type] => utility [patent_app_number] => 16/703916 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 7688 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703916
Capacitorless dram cell Dec 4, 2019 Issued
Array ( [id] => 16773754 [patent_doc_number] => 10984872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Non-volatile memory with source line resistance compensation [patent_app_type] => utility [patent_app_number] => 16/704598 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704598 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704598
Non-volatile memory with source line resistance compensation Dec 4, 2019 Issued
Array ( [id] => 16677034 [patent_doc_number] => 20210065800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => NON-VOLATILE MEMORY DEVICE UTILIZING DUMMY MEMORY BLOCK AS POOL CAPACITOR [patent_app_type] => utility [patent_app_number] => 16/699070 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699070
Non-volatile memory device utilizing dummy memory block as pool capacitor Nov 27, 2019 Issued
Array ( [id] => 16364307 [patent_doc_number] => 20200321058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => PAGE BUFFER, A MEMORY DEVICE HAVING PAGE BUFFER, AND A METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/670764 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670764
Page buffer, a memory device having page buffer, and a method of operating the memory device Oct 30, 2019 Issued
Array ( [id] => 16803114 [patent_doc_number] => 10998065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/670510 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9337 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670510 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670510
Memory device and operating method thereof Oct 30, 2019 Issued
Array ( [id] => 16097909 [patent_doc_number] => 20200202941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => NON-VOLATILE MEMORY CELL COMPLIANT TO A NEAR-MEMORY COMPUTATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/669480 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669480 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669480
Non-volatile memory cell compliant to a near memory computation system Oct 29, 2019 Issued
Array ( [id] => 16943951 [patent_doc_number] => 11056199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Updating corrective read voltage offsets in non-volatile random access memory [patent_app_type] => utility [patent_app_number] => 16/669264 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 16828 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669264
Updating corrective read voltage offsets in non-volatile random access memory Oct 29, 2019 Issued
Array ( [id] => 16668214 [patent_doc_number] => 10937467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Device and method for data-writing [patent_app_type] => utility [patent_app_number] => 16/660588 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660588
Device and method for data-writing Oct 21, 2019 Issued
Array ( [id] => 16339028 [patent_doc_number] => 10789994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Memory architecture having first and second voltages [patent_app_type] => utility [patent_app_number] => 16/660282 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660282 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660282
Memory architecture having first and second voltages Oct 21, 2019 Issued
Array ( [id] => 16746209 [patent_doc_number] => 10971209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => VHSA-VDDSA generator merging scheme [patent_app_type] => utility [patent_app_number] => 16/593576 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5338 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593576 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/593576
VHSA-VDDSA generator merging scheme Oct 3, 2019 Issued
Array ( [id] => 16645337 [patent_doc_number] => 10923201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Memory device and method of operating the memory device [patent_app_type] => utility [patent_app_number] => 16/592338 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/592338
Memory device and method of operating the memory device Oct 2, 2019 Issued
Array ( [id] => 16447958 [patent_doc_number] => 10839889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Apparatuses and methods for providing clocks to data paths [patent_app_type] => utility [patent_app_number] => 16/591566 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591566
Apparatuses and methods for providing clocks to data paths Oct 1, 2019 Issued
Array ( [id] => 15414381 [patent_doc_number] => 20200027513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => OPERATING METHOD OF CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/588222 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588222 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588222
Operating method of controller Sep 29, 2019 Issued
Array ( [id] => 16372208 [patent_doc_number] => 10803974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-13 [patent_title] => Memory device providing bad column repair and method of operating same [patent_app_type] => utility [patent_app_number] => 16/589112 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589112 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589112
Memory device providing bad column repair and method of operating same Sep 29, 2019 Issued
Array ( [id] => 15351121 [patent_doc_number] => 20200013452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => STACK REFRESH CONTROL FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/571043 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571043
Stack refresh control for memory device Sep 12, 2019 Issued
Array ( [id] => 16715385 [patent_doc_number] => 20210082532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SENSING CIRCUITS FOR CHARGE TRAP TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/568394 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568394 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568394
Sensing circuits for charge trap transistors Sep 11, 2019 Issued
Array ( [id] => 16707462 [patent_doc_number] => 10957404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Memory device which generates operation voltages in parallel with reception of an address [patent_app_type] => utility [patent_app_number] => 16/567982 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14266 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567982 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567982
Memory device which generates operation voltages in parallel with reception of an address Sep 10, 2019 Issued
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