Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3632946 [patent_doc_number] => 05594690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator' [patent_app_type] => 1 [patent_app_number] => 8/573306 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 8636 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594690.pdf [firstpage_image] =>[orig_patent_app_number] => 573306 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/573306
Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator Dec 14, 1995 Issued
08/571393 DYNAMIC RANDOM ACCESS MEMORY CELL HAVING INCREASED CAPACITANCE Dec 12, 1995 Abandoned
Array ( [id] => 3727505 [patent_doc_number] => 05617352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Non-volatile, bidirectional, electrically programmable integrated memory element implemented using double polysilicon' [patent_app_type] => 1 [patent_app_number] => 8/572205 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2796 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617352.pdf [firstpage_image] =>[orig_patent_app_number] => 572205 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572205
Non-volatile, bidirectional, electrically programmable integrated memory element implemented using double polysilicon Dec 12, 1995 Issued
Array ( [id] => 3657591 [patent_doc_number] => 05640340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Adjustable cell plate generator' [patent_app_type] => 1 [patent_app_number] => 8/568833 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4135 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640340.pdf [firstpage_image] =>[orig_patent_app_number] => 568833 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/568833
Adjustable cell plate generator Dec 6, 1995 Issued
Array ( [id] => 3715726 [patent_doc_number] => 05654912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Semiconductor memory device with reduced read time and power consumption' [patent_app_type] => 1 [patent_app_number] => 8/568500 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 6887 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654912.pdf [firstpage_image] =>[orig_patent_app_number] => 568500 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/568500
Semiconductor memory device with reduced read time and power consumption Dec 6, 1995 Issued
Array ( [id] => 3657804 [patent_doc_number] => 05638319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Non-volatile random access memory and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 8/567907 [patent_app_country] => US [patent_app_date] => 1995-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 9096 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638319.pdf [firstpage_image] =>[orig_patent_app_number] => 567907 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/567907
Non-volatile random access memory and fabrication method thereof Dec 5, 1995 Issued
Array ( [id] => 3704184 [patent_doc_number] => 05680348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Power supply independent current source for FLASH EPROM erasure' [patent_app_type] => 1 [patent_app_number] => 8/566204 [patent_app_country] => US [patent_app_date] => 1995-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2443 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680348.pdf [firstpage_image] =>[orig_patent_app_number] => 566204 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/566204
Power supply independent current source for FLASH EPROM erasure Nov 30, 1995 Issued
Array ( [id] => 3613044 [patent_doc_number] => 05579272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Semiconductor memory device with data compression test function and its testing method' [patent_app_type] => 1 [patent_app_number] => 8/563797 [patent_app_country] => US [patent_app_date] => 1995-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5724 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579272.pdf [firstpage_image] =>[orig_patent_app_number] => 563797 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563797
Semiconductor memory device with data compression test function and its testing method Nov 27, 1995 Issued
Array ( [id] => 3635355 [patent_doc_number] => 05608687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Output driver control for ROM and RAM devices' [patent_app_type] => 1 [patent_app_number] => 8/563212 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 19927 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608687.pdf [firstpage_image] =>[orig_patent_app_number] => 563212 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563212
Output driver control for ROM and RAM devices Nov 26, 1995 Issued
Array ( [id] => 3703890 [patent_doc_number] => 05661693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Memory device for synchronously reading and writing data' [patent_app_type] => 1 [patent_app_number] => 8/562194 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5867 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661693.pdf [firstpage_image] =>[orig_patent_app_number] => 562194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562194
Memory device for synchronously reading and writing data Nov 21, 1995 Issued
Array ( [id] => 3841383 [patent_doc_number] => 05712820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Multiple word width memory array clocking scheme' [patent_app_type] => 1 [patent_app_number] => 8/559983 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712820.pdf [firstpage_image] =>[orig_patent_app_number] => 559983 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559983
Multiple word width memory array clocking scheme Nov 16, 1995 Issued
Array ( [id] => 3705047 [patent_doc_number] => 05619449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Bit line sensing in a memory array' [patent_app_type] => 1 [patent_app_number] => 8/559695 [patent_app_country] => US [patent_app_date] => 1995-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4759 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619449.pdf [firstpage_image] =>[orig_patent_app_number] => 559695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559695
Bit line sensing in a memory array Nov 14, 1995 Issued
Array ( [id] => 3633025 [patent_doc_number] => 05594695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Sense amplifier control circuit of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/552935 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6511 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594695.pdf [firstpage_image] =>[orig_patent_app_number] => 552935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/552935
Sense amplifier control circuit of semiconductor memory device Nov 2, 1995 Issued
Array ( [id] => 3672514 [patent_doc_number] => 05625599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Semiconductor memory having decoded sense amplifier drive lines' [patent_app_type] => 1 [patent_app_number] => 8/548386 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6548 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625599.pdf [firstpage_image] =>[orig_patent_app_number] => 548386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548386
Semiconductor memory having decoded sense amplifier drive lines Oct 25, 1995 Issued
Array ( [id] => 3630692 [patent_doc_number] => 05615168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method and apparatus for synchronized pipeline data access of a memory system' [patent_app_type] => 1 [patent_app_number] => 8/538085 [patent_app_country] => US [patent_app_date] => 1995-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3822 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615168.pdf [firstpage_image] =>[orig_patent_app_number] => 538085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/538085
Method and apparatus for synchronized pipeline data access of a memory system Oct 1, 1995 Issued
Array ( [id] => 3664394 [patent_doc_number] => 05623437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Circuit having combined level conversion and logic function' [patent_app_type] => 1 [patent_app_number] => 8/532291 [patent_app_country] => US [patent_app_date] => 1995-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5194 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623437.pdf [firstpage_image] =>[orig_patent_app_number] => 532291 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/532291
Circuit having combined level conversion and logic function Sep 21, 1995 Issued
Array ( [id] => 3519119 [patent_doc_number] => 05587959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/530583 [patent_app_country] => US [patent_app_date] => 1995-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 13552 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587959.pdf [firstpage_image] =>[orig_patent_app_number] => 530583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/530583
Semiconductor memory device Sep 18, 1995 Issued
Array ( [id] => 3671723 [patent_doc_number] => 05657288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Efficient addressing of large memories' [patent_app_type] => 1 [patent_app_number] => 8/527389 [patent_app_country] => US [patent_app_date] => 1995-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5915 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657288.pdf [firstpage_image] =>[orig_patent_app_number] => 527389 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/527389
Efficient addressing of large memories Sep 12, 1995 Issued
Array ( [id] => 3657165 [patent_doc_number] => 05629897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal' [patent_app_type] => 1 [patent_app_number] => 8/524927 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 10752 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629897.pdf [firstpage_image] =>[orig_patent_app_number] => 524927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/524927
Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal Sep 7, 1995 Issued
Array ( [id] => 3736432 [patent_doc_number] => 05652722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'System and method for controlling voltage and current characteristics of bit lines in a memory array' [patent_app_type] => 1 [patent_app_number] => 8/519194 [patent_app_country] => US [patent_app_date] => 1995-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8458 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652722.pdf [firstpage_image] =>[orig_patent_app_number] => 519194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519194
System and method for controlling voltage and current characteristics of bit lines in a memory array Aug 24, 1995 Issued
Menu