Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3635355 [patent_doc_number] => 05608687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Output driver control for ROM and RAM devices' [patent_app_type] => 1 [patent_app_number] => 8/563212 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 19927 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608687.pdf [firstpage_image] =>[orig_patent_app_number] => 563212 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563212
Output driver control for ROM and RAM devices Nov 26, 1995 Issued
Array ( [id] => 3703890 [patent_doc_number] => 05661693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Memory device for synchronously reading and writing data' [patent_app_type] => 1 [patent_app_number] => 8/562194 [patent_app_country] => US [patent_app_date] => 1995-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5867 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661693.pdf [firstpage_image] =>[orig_patent_app_number] => 562194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562194
Memory device for synchronously reading and writing data Nov 21, 1995 Issued
Array ( [id] => 3841383 [patent_doc_number] => 05712820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Multiple word width memory array clocking scheme' [patent_app_type] => 1 [patent_app_number] => 8/559983 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712820.pdf [firstpage_image] =>[orig_patent_app_number] => 559983 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559983
Multiple word width memory array clocking scheme Nov 16, 1995 Issued
Array ( [id] => 3705047 [patent_doc_number] => 05619449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Bit line sensing in a memory array' [patent_app_type] => 1 [patent_app_number] => 8/559695 [patent_app_country] => US [patent_app_date] => 1995-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4759 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619449.pdf [firstpage_image] =>[orig_patent_app_number] => 559695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559695
Bit line sensing in a memory array Nov 14, 1995 Issued
Array ( [id] => 3633025 [patent_doc_number] => 05594695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Sense amplifier control circuit of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/552935 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6511 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594695.pdf [firstpage_image] =>[orig_patent_app_number] => 552935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/552935
Sense amplifier control circuit of semiconductor memory device Nov 2, 1995 Issued
Array ( [id] => 3672514 [patent_doc_number] => 05625599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Semiconductor memory having decoded sense amplifier drive lines' [patent_app_type] => 1 [patent_app_number] => 8/548386 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6548 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625599.pdf [firstpage_image] =>[orig_patent_app_number] => 548386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548386
Semiconductor memory having decoded sense amplifier drive lines Oct 25, 1995 Issued
Array ( [id] => 3630692 [patent_doc_number] => 05615168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method and apparatus for synchronized pipeline data access of a memory system' [patent_app_type] => 1 [patent_app_number] => 8/538085 [patent_app_country] => US [patent_app_date] => 1995-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3822 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615168.pdf [firstpage_image] =>[orig_patent_app_number] => 538085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/538085
Method and apparatus for synchronized pipeline data access of a memory system Oct 1, 1995 Issued
Array ( [id] => 3664394 [patent_doc_number] => 05623437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Circuit having combined level conversion and logic function' [patent_app_type] => 1 [patent_app_number] => 8/532291 [patent_app_country] => US [patent_app_date] => 1995-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5194 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623437.pdf [firstpage_image] =>[orig_patent_app_number] => 532291 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/532291
Circuit having combined level conversion and logic function Sep 21, 1995 Issued
Array ( [id] => 3519119 [patent_doc_number] => 05587959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/530583 [patent_app_country] => US [patent_app_date] => 1995-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 13552 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587959.pdf [firstpage_image] =>[orig_patent_app_number] => 530583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/530583
Semiconductor memory device Sep 18, 1995 Issued
Array ( [id] => 3671723 [patent_doc_number] => 05657288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Efficient addressing of large memories' [patent_app_type] => 1 [patent_app_number] => 8/527389 [patent_app_country] => US [patent_app_date] => 1995-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5915 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657288.pdf [firstpage_image] =>[orig_patent_app_number] => 527389 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/527389
Efficient addressing of large memories Sep 12, 1995 Issued
Array ( [id] => 3657165 [patent_doc_number] => 05629897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal' [patent_app_type] => 1 [patent_app_number] => 8/524927 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 10752 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629897.pdf [firstpage_image] =>[orig_patent_app_number] => 524927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/524927
Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal Sep 7, 1995 Issued
Array ( [id] => 3736432 [patent_doc_number] => 05652722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'System and method for controlling voltage and current characteristics of bit lines in a memory array' [patent_app_type] => 1 [patent_app_number] => 8/519194 [patent_app_country] => US [patent_app_date] => 1995-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8458 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652722.pdf [firstpage_image] =>[orig_patent_app_number] => 519194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519194
System and method for controlling voltage and current characteristics of bit lines in a memory array Aug 24, 1995 Issued
Array ( [id] => 3608804 [patent_doc_number] => 05559752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Timing control circuit for synchronous static random access memory' [patent_app_type] => 1 [patent_app_number] => 8/514693 [patent_app_country] => US [patent_app_date] => 1995-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559752.pdf [firstpage_image] =>[orig_patent_app_number] => 514693 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/514693
Timing control circuit for synchronous static random access memory Aug 13, 1995 Issued
Array ( [id] => 3703126 [patent_doc_number] => 05650956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Current amplification type mask-ROM' [patent_app_type] => 1 [patent_app_number] => 8/513384 [patent_app_country] => US [patent_app_date] => 1995-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 5092 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650956.pdf [firstpage_image] =>[orig_patent_app_number] => 513384 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/513384
Current amplification type mask-ROM Aug 10, 1995 Issued
Array ( [id] => 3553197 [patent_doc_number] => 05546018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Fast carry structure with synchronous input' [patent_app_type] => 1 [patent_app_number] => 8/513365 [patent_app_country] => US [patent_app_date] => 1995-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 9259 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546018.pdf [firstpage_image] =>[orig_patent_app_number] => 513365 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/513365
Fast carry structure with synchronous input Aug 8, 1995 Issued
Array ( [id] => 3643956 [patent_doc_number] => 05631864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Memory array having a reduced number of metal source lines' [patent_app_type] => 1 [patent_app_number] => 8/509036 [patent_app_country] => US [patent_app_date] => 1995-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631864.pdf [firstpage_image] =>[orig_patent_app_number] => 509036 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/509036
Memory array having a reduced number of metal source lines Jul 27, 1995 Issued
Array ( [id] => 3697733 [patent_doc_number] => 05663903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Flat-cell read-only memory' [patent_app_type] => 1 [patent_app_number] => 8/508532 [patent_app_country] => US [patent_app_date] => 1995-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2867 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663903.pdf [firstpage_image] =>[orig_patent_app_number] => 508532 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/508532
Flat-cell read-only memory Jul 27, 1995 Issued
Array ( [id] => 3699104 [patent_doc_number] => 05604701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Initializing a read pipeline of a non-volatile sequential memory device' [patent_app_type] => 1 [patent_app_number] => 8/508331 [patent_app_country] => US [patent_app_date] => 1995-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5305 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604701.pdf [firstpage_image] =>[orig_patent_app_number] => 508331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/508331
Initializing a read pipeline of a non-volatile sequential memory device Jul 26, 1995 Issued
Array ( [id] => 3667878 [patent_doc_number] => 05627779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same' [patent_app_type] => 1 [patent_app_number] => 8/505638 [patent_app_country] => US [patent_app_date] => 1995-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 68 [patent_no_of_words] => 19628 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627779.pdf [firstpage_image] =>[orig_patent_app_number] => 505638 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/505638
Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same Jul 20, 1995 Issued
Array ( [id] => 3601555 [patent_doc_number] => 05568438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Sense amplifier with offset autonulling' [patent_app_type] => 1 [patent_app_number] => 8/503529 [patent_app_country] => US [patent_app_date] => 1995-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3872 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568438.pdf [firstpage_image] =>[orig_patent_app_number] => 503529 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/503529
Sense amplifier with offset autonulling Jul 17, 1995 Issued
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