Son Luu Mai

Array ( [id] => 3545147 [patent_doc_number] => 05481206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Circuit for fast carry and logic' [patent_app_type] => 1 [patent_app_number] => 8/310113 [patent_app_country] => US [patent_app_date] => 1994-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 13004 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481206.pdf [firstpage_image] =>[orig_patent_app_number] => 310113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3527105 [patent_doc_number] => 05506806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Memory protection circuit for EPROM' [patent_app_type] => 1 [patent_app_number] => 8/309028 [patent_app_country] => US [patent_app_date] => 1994-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506806.pdf [firstpage_image] =>[orig_patent_app_number] => 309028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3670933 [patent_doc_number] => 05625501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'True image mirror' [patent_app_type] => 1 [patent_app_number] => 8/307557 [patent_app_country] => US [patent_app_date] => 1994-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1088 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625501.pdf [firstpage_image] =>[orig_patent_app_number] => 307557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3515600 [patent_doc_number] => 05515324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'EEPROM having NAND type memory cell array' [patent_app_type] => 1 [patent_app_number] => 8/305333 [patent_app_country] => US [patent_app_date] => 1994-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 6530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515324.pdf [firstpage_image] =>[orig_patent_app_number] => 305333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3527140 [patent_doc_number] => 05506808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Semiconductor memory device and method for reading data' [patent_app_type] => 1 [patent_app_number] => 8/305715 [patent_app_country] => US [patent_app_date] => 1994-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6780 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506808.pdf [firstpage_image] =>[orig_patent_app_number] => 305715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3549645 [patent_doc_number] => 05481497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Semiconductor memory device providing external output data signal in accordance with states of true and complementary read buses' [patent_app_type] => 1 [patent_app_number] => 8/304749 [patent_app_country] => US [patent_app_date] => 1994-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 126 [patent_no_of_words] => 19611 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481497.pdf [firstpage_image] =>[orig_patent_app_number] => 304749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3582573 [patent_doc_number] => 05539699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Flash memory testing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/304583 [patent_app_country] => US [patent_app_date] => 1994-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2826 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539699.pdf [firstpage_image] =>[orig_patent_app_number] => 304583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3598652 [patent_doc_number] => 05517450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Semiconductor memory device with redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 8/302474 [patent_app_country] => US [patent_app_date] => 1994-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 8290 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517450.pdf [firstpage_image] =>[orig_patent_app_number] => 302474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3546765 [patent_doc_number] => 05495439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Semiconductor memory device having SOI structure and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/301755 [patent_app_country] => US [patent_app_date] => 1994-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 51 [patent_no_of_words] => 10709 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495439.pdf [firstpage_image] =>[orig_patent_app_number] => 301755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3502235 [patent_doc_number] => 05537351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Semiconductor memory device carrying out input and output of data in a predetermined bit organization' [patent_app_type] => 1 [patent_app_number] => 8/301754 [patent_app_country] => US [patent_app_date] => 1994-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 8735 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537351.pdf [firstpage_image] =>[orig_patent_app_number] => 301754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3471850 [patent_doc_number] => 05469390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Semiconductor memory system with the function of the replacement to the other chips' [patent_app_type] => 1 [patent_app_number] => 8/301284 [patent_app_country] => US [patent_app_date] => 1994-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 10336 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469390.pdf [firstpage_image] =>[orig_patent_app_number] => 301284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3424895 [patent_doc_number] => 05453949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'BiCMOS Static RAM with active-low word line' [patent_app_type] => 1 [patent_app_number] => 8/298593 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4842 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453949.pdf [firstpage_image] =>[orig_patent_app_number] => 298593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3467391 [patent_doc_number] => 05473567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Disabling sense amplifier' [patent_app_type] => 1 [patent_app_number] => 8/298766 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4691 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473567.pdf [firstpage_image] =>[orig_patent_app_number] => 298766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3438126 [patent_doc_number] => 05463581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Memory in which improvement is made as regards a precharge operation of data readout routes' [patent_app_type] => 1 [patent_app_number] => 8/295076 [patent_app_country] => US [patent_app_date] => 1994-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5546 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463581.pdf [firstpage_image] =>[orig_patent_app_number] => 295076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3600796 [patent_doc_number] => 05488584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Circuit and method for externally controlling signal development in a serial access memory' [patent_app_type] => 1 [patent_app_number] => 8/296397 [patent_app_country] => US [patent_app_date] => 1994-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2244 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488584.pdf [firstpage_image] =>[orig_patent_app_number] => 296397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3586933 [patent_doc_number] => 05524094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Nonvolatile memory device with NAND array' [patent_app_type] => 1 [patent_app_number] => 8/293915 [patent_app_country] => US [patent_app_date] => 1994-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 12349 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524094.pdf [firstpage_image] =>[orig_patent_app_number] => 293915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3525318 [patent_doc_number] => 05487038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-23 [patent_title] => 'Method for read cycle interrupts in a dynamic read-only memory' [patent_app_type] => 1 [patent_app_number] => 8/290549 [patent_app_country] => US [patent_app_date] => 1994-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 19918 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/487/05487038.pdf [firstpage_image] =>[orig_patent_app_number] => 290549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3467306 [patent_doc_number] => 05473562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Method and apparatus for minimizing power-up crowbar current in a retargetable SRAM memory system' [patent_app_type] => 1 [patent_app_number] => 8/286292 [patent_app_country] => US [patent_app_date] => 1994-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5024 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473562.pdf [firstpage_image] =>[orig_patent_app_number] => 286292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3491666 [patent_doc_number] => 05400417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Electro-optic modulator having gated-dither bias control' [patent_app_type] => 1 [patent_app_number] => 8/281712 [patent_app_country] => US [patent_app_date] => 1994-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3752 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/400/05400417.pdf [firstpage_image] =>[orig_patent_app_number] => 281712 [rel_patent_id] =>[rel_patent_doc_number] =>)