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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3424895 [patent_doc_number] => 05453949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'BiCMOS Static RAM with active-low word line' [patent_app_type] => 1 [patent_app_number] => 8/298593 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4842 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453949.pdf [firstpage_image] =>[orig_patent_app_number] => 298593 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/298593
BiCMOS Static RAM with active-low word line Aug 30, 1994 Issued
Array ( [id] => 3600796 [patent_doc_number] => 05488584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Circuit and method for externally controlling signal development in a serial access memory' [patent_app_type] => 1 [patent_app_number] => 8/296397 [patent_app_country] => US [patent_app_date] => 1994-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2244 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488584.pdf [firstpage_image] =>[orig_patent_app_number] => 296397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/296397
Circuit and method for externally controlling signal development in a serial access memory Aug 25, 1994 Issued
Array ( [id] => 3438126 [patent_doc_number] => 05463581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Memory in which improvement is made as regards a precharge operation of data readout routes' [patent_app_type] => 1 [patent_app_number] => 8/295076 [patent_app_country] => US [patent_app_date] => 1994-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5546 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463581.pdf [firstpage_image] =>[orig_patent_app_number] => 295076 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/295076
Memory in which improvement is made as regards a precharge operation of data readout routes Aug 25, 1994 Issued
Array ( [id] => 3586933 [patent_doc_number] => 05524094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Nonvolatile memory device with NAND array' [patent_app_type] => 1 [patent_app_number] => 8/293915 [patent_app_country] => US [patent_app_date] => 1994-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 12349 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524094.pdf [firstpage_image] =>[orig_patent_app_number] => 293915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/293915
Nonvolatile memory device with NAND array Aug 21, 1994 Issued
Array ( [id] => 3525318 [patent_doc_number] => 05487038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-23 [patent_title] => 'Method for read cycle interrupts in a dynamic read-only memory' [patent_app_type] => 1 [patent_app_number] => 8/290549 [patent_app_country] => US [patent_app_date] => 1994-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 19918 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/487/05487038.pdf [firstpage_image] =>[orig_patent_app_number] => 290549 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/290549
Method for read cycle interrupts in a dynamic read-only memory Aug 14, 1994 Issued
Array ( [id] => 3467306 [patent_doc_number] => 05473562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Method and apparatus for minimizing power-up crowbar current in a retargetable SRAM memory system' [patent_app_type] => 1 [patent_app_number] => 8/286292 [patent_app_country] => US [patent_app_date] => 1994-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5024 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473562.pdf [firstpage_image] =>[orig_patent_app_number] => 286292 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/286292
Method and apparatus for minimizing power-up crowbar current in a retargetable SRAM memory system Aug 4, 1994 Issued
08/282148 CIRCUIT STRUCTURE FOR A MEMORY MATRIX AND CORRESPONDING MANUFACTURING METHOD Jul 27, 1994 Abandoned
Array ( [id] => 3491666 [patent_doc_number] => 05400417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Electro-optic modulator having gated-dither bias control' [patent_app_type] => 1 [patent_app_number] => 8/281712 [patent_app_country] => US [patent_app_date] => 1994-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3752 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/400/05400417.pdf [firstpage_image] =>[orig_patent_app_number] => 281712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/281712
Electro-optic modulator having gated-dither bias control Jul 26, 1994 Issued
Array ( [id] => 3451592 [patent_doc_number] => 05430685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Multi-port random access memory device having memory cell rewritable through single input port' [patent_app_type] => 1 [patent_app_number] => 8/270837 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3989 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430685.pdf [firstpage_image] =>[orig_patent_app_number] => 270837 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270837
Multi-port random access memory device having memory cell rewritable through single input port Jul 4, 1994 Issued
Array ( [id] => 3464238 [patent_doc_number] => 05452261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Serial address generator for burst memory' [patent_app_type] => 1 [patent_app_number] => 8/265535 [patent_app_country] => US [patent_app_date] => 1994-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 3667 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452261.pdf [firstpage_image] =>[orig_patent_app_number] => 265535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/265535
Serial address generator for burst memory Jun 23, 1994 Issued
Array ( [id] => 3485423 [patent_doc_number] => 05432729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack' [patent_app_type] => 1 [patent_app_number] => 8/255465 [patent_app_country] => US [patent_app_date] => 1994-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7922 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432729.pdf [firstpage_image] =>[orig_patent_app_number] => 255465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/255465
Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack Jun 7, 1994 Issued
Array ( [id] => 3437071 [patent_doc_number] => 05455791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Method for erasing data in EEPROM devices on SOI substrates and device therefor' [patent_app_type] => 1 [patent_app_number] => 8/252207 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1990 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455791.pdf [firstpage_image] =>[orig_patent_app_number] => 252207 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252207
Method for erasing data in EEPROM devices on SOI substrates and device therefor May 31, 1994 Issued
Array ( [id] => 3114053 [patent_doc_number] => 05448511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Memory stack with an integrated interconnect and mounting structure' [patent_app_type] => 1 [patent_app_number] => 8/252609 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3575 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448511.pdf [firstpage_image] =>[orig_patent_app_number] => 252609 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252609
Memory stack with an integrated interconnect and mounting structure May 31, 1994 Issued
Array ( [id] => 3535007 [patent_doc_number] => 05504734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Optical disc' [patent_app_type] => 1 [patent_app_number] => 8/249970 [patent_app_country] => US [patent_app_date] => 1994-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2645 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504734.pdf [firstpage_image] =>[orig_patent_app_number] => 249970 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/249970
Optical disc May 26, 1994 Issued
08/249771 MONITORING AND ADJUSTING LASER WRITE POWER IN AN OPTICAL DISK RECORDER USING PULSE-WIDTH MODULATED POWER LEVEL CHECKING SIGNALS May 25, 1994 Abandoned
08/243585 SEMICONDUCTOR MEMORY DEVICE May 15, 1994 Abandoned
Array ( [id] => 3915249 [patent_doc_number] => 05898619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Memory cell having a plural transistor transmission gate and method of formation' [patent_app_type] => 1 [patent_app_number] => 8/242993 [patent_app_country] => US [patent_app_date] => 1994-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 5461 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898619.pdf [firstpage_image] =>[orig_patent_app_number] => 242993 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/242993
Memory cell having a plural transistor transmission gate and method of formation May 15, 1994 Issued
Array ( [id] => 3529905 [patent_doc_number] => 05530672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Integrated circuit for operation with plural supply voltages' [patent_app_type] => 1 [patent_app_number] => 8/239604 [patent_app_country] => US [patent_app_date] => 1994-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3055 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530672.pdf [firstpage_image] =>[orig_patent_app_number] => 239604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/239604
Integrated circuit for operation with plural supply voltages May 8, 1994 Issued
Array ( [id] => 3120487 [patent_doc_number] => 05465231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'EEPROM and logic LSI chip including such EEPROM' [patent_app_type] => 1 [patent_app_number] => 8/239078 [patent_app_country] => US [patent_app_date] => 1994-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4410 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465231.pdf [firstpage_image] =>[orig_patent_app_number] => 239078 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/239078
EEPROM and logic LSI chip including such EEPROM May 5, 1994 Issued
Array ( [id] => 3425211 [patent_doc_number] => 05453969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Optical memory with pit depth encoding' [patent_app_type] => 1 [patent_app_number] => 8/238756 [patent_app_country] => US [patent_app_date] => 1994-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3403 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453969.pdf [firstpage_image] =>[orig_patent_app_number] => 238756 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/238756
Optical memory with pit depth encoding May 3, 1994 Issued
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