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Array ( [id] => 3131023 [patent_doc_number] => 05384741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring' [patent_app_type] => 1 [patent_app_number] => 8/186955 [patent_app_country] => US [patent_app_date] => 1994-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6095 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384741.pdf [firstpage_image] =>[orig_patent_app_number] => 186955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3124625 [patent_doc_number] => 05396449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Fast content addressable memory with reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 8/171483 [patent_app_country] => US [patent_app_date] => 1993-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2747 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396449.pdf [firstpage_image] =>[orig_patent_app_number] => 171483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3435715 [patent_doc_number] => 05416743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Databus architecture for accelerated column access in RAM' [patent_app_type] => 1 [patent_app_number] => 8/164703 [patent_app_country] => US [patent_app_date] => 1993-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3293 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416743.pdf [firstpage_image] =>[orig_patent_app_number] => 164703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3624133 [patent_doc_number] => 05511026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Boosted and regulated gate power supply with reference tracking for multi-density and low voltage supply memories' [patent_app_type] => 1 [patent_app_number] => 8/160578 [patent_app_country] => US [patent_app_date] => 1993-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 10 [patent_no_of_words] => 5141 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511026.pdf [firstpage_image] =>[orig_patent_app_number] => 160578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3103866 [patent_doc_number] => 05369610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-29 [patent_title] => 'Static memory with improved write-recovery' [patent_app_type] => 1 [patent_app_number] => 8/157401 [patent_app_country] => US [patent_app_date] => 1993-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3000 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/369/05369610.pdf [firstpage_image] =>[orig_patent_app_number] => 157401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3418993 [patent_doc_number] => 05461585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Semiconductor integrated circuit having delay circuit with voltage-to-delay characteristics proportional to power voltage level' [patent_app_type] => 1 [patent_app_number] => 8/157296 [patent_app_country] => US [patent_app_date] => 1993-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4679 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/461/05461585.pdf [firstpage_image] =>[orig_patent_app_number] => 157296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3124917 [patent_doc_number] => 05396465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Circuit for controlling isolation transistors in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/156779 [patent_app_country] => US [patent_app_date] => 1993-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2512 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396465.pdf [firstpage_image] =>[orig_patent_app_number] => 156779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3468514 [patent_doc_number] => 05383155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'Data output latch control circuit and process for semiconductor memory system' [patent_app_type] => 1 [patent_app_number] => 8/148601 [patent_app_country] => US [patent_app_date] => 1993-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3289 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/383/05383155.pdf [firstpage_image] =>[orig_patent_app_number] => 148601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3470928 [patent_doc_number] => 05392248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Circuit and method for detecting column-line shorts in integrated-circuit memories' [patent_app_type] => 1 [patent_app_number] => 8/149242 [patent_app_country] => US [patent_app_date] => 1993-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2006 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392248.pdf [firstpage_image] =>[orig_patent_app_number] => 149242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3451873 [patent_doc_number] => 05430704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Reproducing system for an optical disc' [patent_app_type] => 1 [patent_app_number] => 8/138445 [patent_app_country] => US [patent_app_date] => 1993-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2311 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430704.pdf [firstpage_image] =>[orig_patent_app_number] => 138445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3482917 [patent_doc_number] => 05477526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Optical disk substrate and optical disk employing said optical disk substrate' [patent_app_type] => 1 [patent_app_number] => 8/137985 [patent_app_country] => US [patent_app_date] => 1993-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 10553 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477526.pdf [firstpage_image] =>[orig_patent_app_number] => 137985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3485581 [patent_doc_number] => 05432740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure' [patent_app_type] => 1 [patent_app_number] => 8/135813 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5972 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432740.pdf [firstpage_image] =>[orig_patent_app_number] => 135813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122833 [patent_doc_number] => 05414660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Double word line type dynamic RAM having redundant sub-array of cells' [patent_app_type] => 1 [patent_app_number] => 8/129854 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1570 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414660.pdf [firstpage_image] =>[orig_patent_app_number] => 129854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3006631 [patent_doc_number] => 05363333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Dynamic random access memory device having power supply system appropriately biasing switching transistors and storage capacitors in burn-in testing process' [patent_app_type] => 1 [patent_app_number] => 8/129375 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 8240 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 587 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/363/05363333.pdf [firstpage_image] =>[orig_patent_app_number] => 129375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3463120 [patent_doc_number] => 05379260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Memory cell having a super supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/128895 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2435 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379260.pdf [firstpage_image] =>[orig_patent_app_number] => 128895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3459378 [patent_doc_number] => 05424987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Semiconductor memory device having redundant memory cells and circuit therefor' [patent_app_type] => 1 [patent_app_number] => 8/128237 [patent_app_country] => US [patent_app_date] => 1993-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3980 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424987.pdf [firstpage_image] =>[orig_patent_app_number] => 128237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3454377 [patent_doc_number] => 05388084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Non-volatile semiconductor memory device with high voltage generator' [patent_app_type] => 1 [patent_app_number] => 8/128087 [patent_app_country] => US [patent_app_date] => 1993-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 9236 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388084.pdf [firstpage_image] =>[orig_patent_app_number] => 128087 [rel_patent_id] =>[rel_patent_doc_number] =>)