Son Luu Mai

Array ( [id] => 3468514 [patent_doc_number] => 05383155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'Data output latch control circuit and process for semiconductor memory system' [patent_app_type] => 1 [patent_app_number] => 8/148601 [patent_app_country] => US [patent_app_date] => 1993-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3289 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/383/05383155.pdf [firstpage_image] =>[orig_patent_app_number] => 148601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3470928 [patent_doc_number] => 05392248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Circuit and method for detecting column-line shorts in integrated-circuit memories' [patent_app_type] => 1 [patent_app_number] => 8/149242 [patent_app_country] => US [patent_app_date] => 1993-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2006 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392248.pdf [firstpage_image] =>[orig_patent_app_number] => 149242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3451873 [patent_doc_number] => 05430704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Reproducing system for an optical disc' [patent_app_type] => 1 [patent_app_number] => 8/138445 [patent_app_country] => US [patent_app_date] => 1993-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2311 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430704.pdf [firstpage_image] =>[orig_patent_app_number] => 138445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3482917 [patent_doc_number] => 05477526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Optical disk substrate and optical disk employing said optical disk substrate' [patent_app_type] => 1 [patent_app_number] => 8/137985 [patent_app_country] => US [patent_app_date] => 1993-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 10553 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477526.pdf [firstpage_image] =>[orig_patent_app_number] => 137985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3485581 [patent_doc_number] => 05432740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure' [patent_app_type] => 1 [patent_app_number] => 8/135813 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5972 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432740.pdf [firstpage_image] =>[orig_patent_app_number] => 135813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3006631 [patent_doc_number] => 05363333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Dynamic random access memory device having power supply system appropriately biasing switching transistors and storage capacitors in burn-in testing process' [patent_app_type] => 1 [patent_app_number] => 8/129375 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 8240 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 587 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/363/05363333.pdf [firstpage_image] =>[orig_patent_app_number] => 129375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3463120 [patent_doc_number] => 05379260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Memory cell having a super supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/128895 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2435 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379260.pdf [firstpage_image] =>[orig_patent_app_number] => 128895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122833 [patent_doc_number] => 05414660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Double word line type dynamic RAM having redundant sub-array of cells' [patent_app_type] => 1 [patent_app_number] => 8/129854 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1570 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414660.pdf [firstpage_image] =>[orig_patent_app_number] => 129854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3454377 [patent_doc_number] => 05388084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Non-volatile semiconductor memory device with high voltage generator' [patent_app_type] => 1 [patent_app_number] => 8/128087 [patent_app_country] => US [patent_app_date] => 1993-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 9236 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388084.pdf [firstpage_image] =>[orig_patent_app_number] => 128087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3459378 [patent_doc_number] => 05424987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Semiconductor memory device having redundant memory cells and circuit therefor' [patent_app_type] => 1 [patent_app_number] => 8/128237 [patent_app_country] => US [patent_app_date] => 1993-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3980 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424987.pdf [firstpage_image] =>[orig_patent_app_number] => 128237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3006670 [patent_doc_number] => 05363335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Nonvolatile memory with automatic power supply configuration' [patent_app_type] => 1 [patent_app_number] => 8/127943 [patent_app_country] => US [patent_app_date] => 1993-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6864 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/363/05363335.pdf [firstpage_image] =>[orig_patent_app_number] => 127943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3123028 [patent_doc_number] => 05414672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Semiconductor memory device including address transition detector' [patent_app_type] => 1 [patent_app_number] => 8/126763 [patent_app_country] => US [patent_app_date] => 1993-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4043 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414672.pdf [firstpage_image] =>[orig_patent_app_number] => 126763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3588254 [patent_doc_number] => 05491664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'Flexibilitiy for column redundancy in a divided array architecture' [patent_app_type] => 1 [patent_app_number] => 8/127241 [patent_app_country] => US [patent_app_date] => 1993-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3963 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491664.pdf [firstpage_image] =>[orig_patent_app_number] => 127241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3462919 [patent_doc_number] => 05379247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Semiconductor memory device including memory cells connected to a ground line' [patent_app_type] => 1 [patent_app_number] => 8/126765 [patent_app_country] => US [patent_app_date] => 1993-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 7887 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379247.pdf [firstpage_image] =>[orig_patent_app_number] => 126765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122816 [patent_doc_number] => 05414659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Semiconductor memory device having address transition detector quickly enabling redundancy decoder' [patent_app_type] => 1 [patent_app_number] => 8/123258 [patent_app_country] => US [patent_app_date] => 1993-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8266 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414659.pdf [firstpage_image] =>[orig_patent_app_number] => 123258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3500842 [patent_doc_number] => 05561622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Integrated memory cube structure' [patent_app_type] => 1 [patent_app_number] => 8/120993 [patent_app_country] => US [patent_app_date] => 1993-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5471 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561622.pdf [firstpage_image] =>[orig_patent_app_number] => 120993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3033680 [patent_doc_number] => 05349250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Logic structure and circuit for fast carry' [patent_app_type] => 1 [patent_app_number] => 8/116659 [patent_app_country] => US [patent_app_date] => 1993-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 10977 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349250.pdf [firstpage_image] =>[orig_patent_app_number] => 116659 [rel_patent_id] =>[rel_patent_doc_number] =>)