Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14541759 [patent_doc_number] => 20190206501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/107008 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107008 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107008
Memory system and operating method thereof Aug 20, 2018 Issued
Array ( [id] => 16463835 [patent_doc_number] => 10847189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-24 [patent_title] => Voltage regulator for generation of a voltage for a RAM cell [patent_app_type] => utility [patent_app_number] => 16/107720 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6927 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107720 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107720
Voltage regulator for generation of a voltage for a RAM cell Aug 20, 2018 Issued
Array ( [id] => 15563817 [patent_doc_number] => 20200066320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => SYSTEM FOR A WIDE TEMPERATURE RANGE NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/107352 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107352
System for a wide temperature range nonvolatile memory Aug 20, 2018 Issued
Array ( [id] => 15580201 [patent_doc_number] => 10580492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => System and method for implementing configurable convoluted neural networks with flash memories [patent_app_type] => utility [patent_app_number] => 16/107282 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 45 [patent_no_of_words] => 10102 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107282 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107282
System and method for implementing configurable convoluted neural networks with flash memories Aug 20, 2018 Issued
Array ( [id] => 15388405 [patent_doc_number] => 10535397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-14 [patent_title] => Sensing techniques for multi-level cells [patent_app_type] => utility [patent_app_number] => 16/107280 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 20058 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107280 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107280
Sensing techniques for multi-level cells Aug 20, 2018 Issued
Array ( [id] => 15984301 [patent_doc_number] => 10672486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Refreshing data stored at a memory component based on a memory component characteristic component [patent_app_type] => utility [patent_app_number] => 16/107878 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9677 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107878 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107878
Refreshing data stored at a memory component based on a memory component characteristic component Aug 20, 2018 Issued
Array ( [id] => 15856761 [patent_doc_number] => 10643673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Apparatuses and methods for performing compare operations using sensing circuitry [patent_app_type] => utility [patent_app_number] => 16/105543 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6248 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105543 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105543
Apparatuses and methods for performing compare operations using sensing circuitry Aug 19, 2018 Issued
Array ( [id] => 15249731 [patent_doc_number] => 10510392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-17 [patent_title] => Integrated circuits having memory cells with shared bit lines and shared source lines [patent_app_type] => utility [patent_app_number] => 16/047882 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4894 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047882 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047882
Integrated circuits having memory cells with shared bit lines and shared source lines Jul 26, 2018 Issued
Array ( [id] => 15108325 [patent_doc_number] => 10475492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-12 [patent_title] => Circuit and method for read latency control [patent_app_type] => utility [patent_app_number] => 16/047550 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7594 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047550 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047550
Circuit and method for read latency control Jul 26, 2018 Issued
Array ( [id] => 15703037 [patent_doc_number] => 10607705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Memory device including a deterioration level detection circuit [patent_app_type] => utility [patent_app_number] => 16/047384 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8251 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047384
Memory device including a deterioration level detection circuit Jul 26, 2018 Issued
Array ( [id] => 15077211 [patent_doc_number] => 10468100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-05 [patent_title] => Detecting method for a resistive random access memory cell [patent_app_type] => utility [patent_app_number] => 16/046966 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4804 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046966 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046966
Detecting method for a resistive random access memory cell Jul 25, 2018 Issued
Array ( [id] => 14671515 [patent_doc_number] => 10373672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Command signal clock gating [patent_app_type] => utility [patent_app_number] => 16/039995 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5347 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039995
Command signal clock gating Jul 18, 2018 Issued
Array ( [id] => 14349795 [patent_doc_number] => 20190156870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => DATA OUTPUT CIRCUIT, MEMORY DEVICE INCLUDING THE DATA OUTPUT CIRCUIT, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/031408 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031408 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031408
Data output circuit, memory device including the data output circuit, and operating method of the memory device Jul 9, 2018 Issued
Array ( [id] => 15215015 [patent_doc_number] => 20190370194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 16/030746 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030746 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030746
Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same Jul 8, 2018 Issued
Array ( [id] => 13527829 [patent_doc_number] => 20180315457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => APPARATUSES AND METHODS FOR CONTROLLING WORDLINES AND SENSE AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 16/029046 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029046
Apparatuses and methods for controlling wordlines and sense amplifiers Jul 5, 2018 Issued
Array ( [id] => 13527853 [patent_doc_number] => 20180315469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => STACK REFRESH CONTROL FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/026559 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/026559
Stack refresh control for memory device Jul 2, 2018 Issued
Array ( [id] => 13629285 [patent_doc_number] => 20180366195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => METHOD, SYSTEM AND DEVICE FOR COMPLEMENTARY NON-VOLATILE MEMORY DEVICE OPERATION [patent_app_type] => utility [patent_app_number] => 16/017755 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017755
Method, system and device for complementary non-volatile memory device operation Jun 24, 2018 Issued
Array ( [id] => 14349791 [patent_doc_number] => 20190156868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/015808 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/015808
Semiconductor memory device Jun 21, 2018 Issued
Array ( [id] => 14954789 [patent_doc_number] => 10438671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-08 [patent_title] => Reducing program disturb by modifying word line voltages at interface in two-tier stack during programming [patent_app_type] => utility [patent_app_number] => 16/015612 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 18838 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/015612
Reducing program disturb by modifying word line voltages at interface in two-tier stack during programming Jun 21, 2018 Issued
Array ( [id] => 16858101 [patent_doc_number] => 20210158846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/625826 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625826 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625826
Memory device comprising first through fourth transistors Jun 18, 2018 Issued
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