Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14889357 [patent_doc_number] => 10424730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Tapered memory cell profiles [patent_app_type] => utility [patent_app_number] => 15/893106 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 13452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15893106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/893106
Tapered memory cell profiles Feb 8, 2018 Issued
Array ( [id] => 14177429 [patent_doc_number] => 10262735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Devices and methods to program a memory cell [patent_app_type] => utility [patent_app_number] => 15/881491 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881491 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881491
Devices and methods to program a memory cell Jan 25, 2018 Issued
Array ( [id] => 14035985 [patent_doc_number] => 10229745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Suppression of program disturb with bit line and select gate voltage regulation [patent_app_type] => utility [patent_app_number] => 15/877633 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877633 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/877633
Suppression of program disturb with bit line and select gate voltage regulation Jan 22, 2018 Issued
Array ( [id] => 16738705 [patent_doc_number] => 10964366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Magnetic memory, recording method of magnetic memory, and reading method of magnetic memory [patent_app_type] => utility [patent_app_number] => 16/490142 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11719 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16490142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/490142
Magnetic memory, recording method of magnetic memory, and reading method of magnetic memory Jan 4, 2018 Issued
Array ( [id] => 13769015 [patent_doc_number] => 10176854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Memory decoding system [patent_app_type] => utility [patent_app_number] => 15/860268 [patent_app_country] => US [patent_app_date] => 2018-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15860268 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/860268
Memory decoding system Jan 1, 2018 Issued
Array ( [id] => 12758872 [patent_doc_number] => 20180144792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => Memory Cells, Memory Systems, and Memory Programming Methods [patent_app_type] => utility [patent_app_number] => 15/858201 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858201 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858201
Memory cells, memory systems, and memory programming methods Dec 28, 2017 Issued
Array ( [id] => 14541661 [patent_doc_number] => 20190206452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => TEMPERATURE-BASED MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/857704 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857704 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857704
Temperature-based memory operations Dec 28, 2017 Issued
Array ( [id] => 14541735 [patent_doc_number] => 20190206489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => POLARITY-CONDITIONED MEMORY CELL WRITE OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/857188 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857188 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857188
Polarity-conditioned memory cell write operations Dec 27, 2017 Issued
Array ( [id] => 14768621 [patent_doc_number] => 10395711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Perpendicular source and bit lines for an MRAM array [patent_app_type] => utility [patent_app_number] => 15/857220 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7128 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857220
Perpendicular source and bit lines for an MRAM array Dec 27, 2017 Issued
Array ( [id] => 14616517 [patent_doc_number] => 10360962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-23 [patent_title] => Memory array with individually trimmable sense amplifiers [patent_app_type] => utility [patent_app_number] => 15/857296 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5995 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857296 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857296
Memory array with individually trimmable sense amplifiers Dec 27, 2017 Issued
Array ( [id] => 14768623 [patent_doc_number] => 10395712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Memory array with horizontal source line and sacrificial bitline per virtual source [patent_app_type] => utility [patent_app_number] => 15/857264 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857264 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857264
Memory array with horizontal source line and sacrificial bitline per virtual source Dec 27, 2017 Issued
Array ( [id] => 13950313 [patent_doc_number] => 10210935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Associative row decoder [patent_app_type] => utility [patent_app_number] => 15/854867 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4174 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854867 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854867
Associative row decoder Dec 26, 2017 Issued
Array ( [id] => 14093621 [patent_doc_number] => 10242723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-26 [patent_title] => Method and apparatus for background memory subsystem calibration [patent_app_type] => utility [patent_app_number] => 15/846992 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846992 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/846992
Method and apparatus for background memory subsystem calibration Dec 18, 2017 Issued
Array ( [id] => 14491577 [patent_doc_number] => 10332586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Apparatuses and methods for subrow addressing [patent_app_type] => utility [patent_app_number] => 15/846410 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11456 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846410 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/846410
Apparatuses and methods for subrow addressing Dec 18, 2017 Issued
Array ( [id] => 14267241 [patent_doc_number] => 10283190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-07 [patent_title] => Transpose non-volatile (NV) memory (NVM) bit cells and related data arrays configured for row and column, transpose access operations [patent_app_type] => utility [patent_app_number] => 15/845722 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 17657 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845722 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845722
Transpose non-volatile (NV) memory (NVM) bit cells and related data arrays configured for row and column, transpose access operations Dec 17, 2017 Issued
Array ( [id] => 14525453 [patent_doc_number] => 10339997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-02 [patent_title] => Multi-phase clock division [patent_app_type] => utility [patent_app_number] => 15/845874 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7424 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845874
Multi-phase clock division Dec 17, 2017 Issued
Array ( [id] => 13754487 [patent_doc_number] => 10170195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-01 [patent_title] => Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads [patent_app_type] => utility [patent_app_number] => 15/833720 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833720 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/833720
Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads Dec 5, 2017 Issued
Array ( [id] => 14332577 [patent_doc_number] => 10297312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Resistive memory cell programmed by metal alloy formation and method of operating thereof [patent_app_type] => utility [patent_app_number] => 15/833192 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 37 [patent_no_of_words] => 20370 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/833192
Resistive memory cell programmed by metal alloy formation and method of operating thereof Dec 5, 2017 Issued
Array ( [id] => 14459353 [patent_doc_number] => 10325647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Non-volatile SRAM cell using resistive memory elements [patent_app_type] => utility [patent_app_number] => 15/833802 [patent_app_country] => US [patent_app_date] => 2017-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8112 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15833802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/833802
Non-volatile SRAM cell using resistive memory elements Dec 5, 2017 Issued
Array ( [id] => 12895498 [patent_doc_number] => 20180190341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => MEMORY DEVICE FOR CONTROLLING REFRESHING OPERATION [patent_app_type] => utility [patent_app_number] => 15/830314 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830314 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/830314
Memory device for controlling refreshing operation Dec 3, 2017 Issued
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