Search

Son Luu Mai

Examiner (ID: 3402, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19828772 [patent_doc_number] => 12249564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Package structure, RDL structure comprising redistribution layer having ground plates and signal lines [patent_app_type] => utility [patent_app_number] => 18/306194 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306194 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306194
Package structure, RDL structure comprising redistribution layer having ground plates and signal lines Apr 23, 2023 Issued
Array ( [id] => 18555292 [patent_doc_number] => 20230253309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/133970 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18133970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/133970
Interconnect structure and method for forming the same Apr 11, 2023 Issued
Array ( [id] => 20532287 [patent_doc_number] => 12550740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Chip packaging structure and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 18/132560 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/132560
Chip packaging structure and method for manufacturing same Apr 9, 2023 Issued
Array ( [id] => 20509309 [patent_doc_number] => 12543603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 18/132749 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 2279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132749 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/132749
Semiconductor package Apr 9, 2023 Issued
Array ( [id] => 19500408 [patent_doc_number] => 20240339426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => LEADLESS SEMICONDUCTOR PACKAGE WITH DUAL-SIDED STUD STRUCTURE FOR DIE-TO-PACKAGE FAN OUT [patent_app_type] => utility [patent_app_number] => 18/131929 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18131929 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/131929
LEADLESS SEMICONDUCTOR PACKAGE WITH DUAL-SIDED STUD STRUCTURE FOR DIE-TO-PACKAGE FAN OUT Apr 6, 2023 Pending
Array ( [id] => 18833892 [patent_doc_number] => 20230402419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => INTEGRATED CIRCUIT, DATA DRIVING APPARATUS, AND CHIP-ON-FILM PACKAGE [patent_app_type] => utility [patent_app_number] => 18/296765 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18296765 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/296765
INTEGRATED CIRCUIT, DATA DRIVING APPARATUS, AND CHIP-ON-FILM PACKAGE Apr 5, 2023 Issued
Array ( [id] => 19409118 [patent_doc_number] => 20240292629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/296182 [patent_app_country] => US [patent_app_date] => 2023-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18296182 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/296182
THREE-DIMENSIONAL MEMORY DEVICES Apr 4, 2023 Pending
Array ( [id] => 18540842 [patent_doc_number] => 20230245953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => POWER MODULE AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/295942 [patent_app_country] => US [patent_app_date] => 2023-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295942 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295942
Power module and related methods Apr 4, 2023 Issued
Array ( [id] => 19500399 [patent_doc_number] => 20240339417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => MAGNETIC SHIELDING FOR MAGNETO RESISTIVE MEMORY [patent_app_type] => utility [patent_app_number] => 18/295518 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295518 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295518
MAGNETIC SHIELDING FOR MAGNETO RESISTIVE MEMORY Apr 3, 2023 Pending
Array ( [id] => 19484171 [patent_doc_number] => 20240332213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => PROTRUDED SCRIBE FEATURE DELAMINATION MITIGATION [patent_app_type] => utility [patent_app_number] => 18/194512 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194512
Protruded scribe feature delamination mitigation Mar 30, 2023 Issued
Array ( [id] => 19269500 [patent_doc_number] => 20240213204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => CIRCUIT BOARD, MANUFACTURING METHOD THEREOF, AND ELECTRONIC COMPONENT PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/127235 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18127235 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/127235
CIRCUIT BOARD, MANUFACTURING METHOD THEREOF, AND ELECTRONIC COMPONENT PACKAGE INCLUDING THE SAME Mar 27, 2023 Pending
Array ( [id] => 18680044 [patent_doc_number] => 20230317702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => Large-Scale Interleaved Transmitters and Receivers Heterogeneously Integrated on a Common Substrate [patent_app_type] => utility [patent_app_number] => 18/191308 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/191308
Large-Scale Interleaved Transmitters and Receivers Heterogeneously Integrated on a Common Substrate Mar 27, 2023 Pending
Array ( [id] => 19654482 [patent_doc_number] => 12176282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Manufacturing method of semiconductor package [patent_app_type] => utility [patent_app_number] => 18/190935 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 9996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190935
Manufacturing method of semiconductor package Mar 26, 2023 Issued
Array ( [id] => 19943682 [patent_doc_number] => 12315818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Interconnection structure of a semiconductor chip having pads of different widths and semiconductor package including the interconnection structure [patent_app_type] => utility [patent_app_number] => 18/126759 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 3183 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126759
Interconnection structure of a semiconductor chip having pads of different widths and semiconductor package including the interconnection structure Mar 26, 2023 Issued
Array ( [id] => 20532336 [patent_doc_number] => 12550790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Stacked integrated circuit (IC) package [patent_app_type] => utility [patent_app_number] => 18/184029 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184029
Stacked integrated circuit (IC) package Mar 14, 2023 Issued
Array ( [id] => 20334468 [patent_doc_number] => 12464764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Low parasitic capacitance contact structure [patent_app_type] => utility [patent_app_number] => 18/182910 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182910 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182910
Low parasitic capacitance contact structure Mar 12, 2023 Issued
Array ( [id] => 18759837 [patent_doc_number] => 11810876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-07 [patent_title] => Heterogeneous integration of radio frequency transistor chiplets having interconnection tuning circuits [patent_app_type] => utility [patent_app_number] => 18/182314 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182314 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182314
Heterogeneous integration of radio frequency transistor chiplets having interconnection tuning circuits Mar 9, 2023 Issued
Array ( [id] => 19837675 [patent_doc_number] => 20250089461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => Display Substrate and Display Device [patent_app_type] => utility [patent_app_number] => 18/289099 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18289099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/289099
Display Substrate and Display Device Feb 26, 2023 Pending
Array ( [id] => 18458806 [patent_doc_number] => 20230200088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/113070 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113070
Magnetoresistive random access memory and method for fabricating the same Feb 22, 2023 Issued
Array ( [id] => 19305791 [patent_doc_number] => 20240234371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/171672 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171672
CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Feb 20, 2023 Pending
Menu