Son Luu Mai

Array ( [id] => 6475099 [patent_doc_number] => 20100008176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Write Leveling Of Memory Units Designed To Receive Access Requests In A Sequential Chained Topology' [patent_app_type] => utility [patent_app_number] => 12/169662 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20100008176.pdf [firstpage_image] =>[orig_patent_app_number] => 12169662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5308842 [patent_doc_number] => 20090016123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/168986 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5823 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016123.pdf [firstpage_image] =>[orig_patent_app_number] => 12168986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16062 [patent_doc_number] => 07808841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Data output circuit for semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/169568 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4442 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808841.pdf [firstpage_image] =>[orig_patent_app_number] => 12169568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16073 [patent_doc_number] => 07808849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Read leveling of memory units designed to receive access requests in a sequential chained topology' [patent_app_type] => utility [patent_app_number] => 12/168948 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4215 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808849.pdf [firstpage_image] =>[orig_patent_app_number] => 12168948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7049 [patent_doc_number] => 07813201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Differential sense amplifier' [patent_app_type] => utility [patent_app_number] => 12/169534 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4047 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/813/07813201.pdf [firstpage_image] =>[orig_patent_app_number] => 12169534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6491541 [patent_doc_number] => 20100214826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'MAGNETIC RANDOM ACCESS MEMORY, WRITE METHOD THEREFOR, AND MAGNETORESISTANCE EFFECT ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/678538 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 17361 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20100214826.pdf [firstpage_image] =>[orig_patent_app_number] => 12678538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 237050 [patent_doc_number] => 07596033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/216489 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 17216 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596033.pdf [firstpage_image] =>[orig_patent_app_number] => 12216489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6605886 [patent_doc_number] => 20100002505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'READING METHOD FOR MLC MEMORY AND READING CIRCUIT USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/167265 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3851 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20100002505.pdf [firstpage_image] =>[orig_patent_app_number] => 12167265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5295160 [patent_doc_number] => 20090010086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/167396 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8281 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20090010086.pdf [firstpage_image] =>[orig_patent_app_number] => 12167396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4584481 [patent_doc_number] => 07826262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Operation method of nitride-based flash memory and method of reducing coupling interference' [patent_app_type] => utility [patent_app_number] => 12/167464 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3886 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826262.pdf [firstpage_image] =>[orig_patent_app_number] => 12167464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6618 [patent_doc_number] => 07817481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Column selectable self-biasing virtual voltages for SRAM write assist' [patent_app_type] => utility [patent_app_number] => 12/167300 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3982 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/817/07817481.pdf [firstpage_image] =>[orig_patent_app_number] => 12167300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4590493 [patent_doc_number] => 07852683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Correcting for over programming non-volatile storage' [patent_app_type] => utility [patent_app_number] => 12/167128 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 33 [patent_no_of_words] => 14693 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/852/07852683.pdf [firstpage_image] =>[orig_patent_app_number] => 12167128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7590409 [patent_doc_number] => 07663950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Method for column redundancy using data latches in solid-state memories' [patent_app_type] => utility [patent_app_number] => 12/163017 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 9995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663950.pdf [firstpage_image] =>[orig_patent_app_number] => 12163017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4581032 [patent_doc_number] => 07855908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Information storage devices using magnetic domain wall motion and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 12/213856 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7945 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/855/07855908.pdf [firstpage_image] =>[orig_patent_app_number] => 12213856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4858089 [patent_doc_number] => 20080266939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Magnetic memory device' [patent_app_type] => utility [patent_app_number] => 12/213505 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6478 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266939.pdf [firstpage_image] =>[orig_patent_app_number] => 12213505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5347742 [patent_doc_number] => 20090003103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY TESTER' [patent_app_type] => utility [patent_app_number] => 12/142278 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12666 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20090003103.pdf [firstpage_image] =>[orig_patent_app_number] => 12142278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 55602 [patent_doc_number] => 07773441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Memory malfunction prediction system and method' [patent_app_type] => utility [patent_app_number] => 12/141716 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2956 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773441.pdf [firstpage_image] =>[orig_patent_app_number] => 12141716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5359518 [patent_doc_number] => 20090034312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'SINGLE-EVENT UPSET IMMUNE STATIC RANDOM ACCESS MEMORY CELL CIRCUIT, SYSTEM, AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/141900 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4891 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20090034312.pdf [firstpage_image] =>[orig_patent_app_number] => 12141900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4851055 [patent_doc_number] => 20080316797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Memory Element Array' [patent_app_type] => utility [patent_app_number] => 12/141492 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5079 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20080316797.pdf [firstpage_image] =>[orig_patent_app_number] => 12141492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4674747 [patent_doc_number] => 20080212375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'METHOD OF PROGRAMMING AND ERASING A P-CHANNEL BE-SONOS NAND FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 12/121791 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5569 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20080212375.pdf [firstpage_image] =>[orig_patent_app_number] => 12121791 [rel_patent_id] =>[rel_patent_doc_number] =>)