
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4766730
[patent_doc_number] => 20080177942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-24
[patent_title] => '276-PIN BUFFERED MEMORY MODULE WITH ENHANCED FAULT TOLERANCE'
[patent_app_type] => utility
[patent_app_number] => 12/060998
[patent_app_country] => US
[patent_app_date] => 2008-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6619
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20080177942.pdf
[firstpage_image] =>[orig_patent_app_number] => 12060998
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/060998 | 276-pin buffered memory module with enhanced fault tolerance | Apr 1, 2008 | Issued |
Array
(
[id] => 15711
[patent_doc_number] => 07804710
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-28
[patent_title] => 'Multi-layer magnetic random access memory using spin-torque magnetic tunnel junctions and method for write state of the multi-layer magnetic random access memory'
[patent_app_type] => utility
[patent_app_number] => 12/059504
[patent_app_country] => US
[patent_app_date] => 2008-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 5177
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/804/07804710.pdf
[firstpage_image] =>[orig_patent_app_number] => 12059504
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/059504 | Multi-layer magnetic random access memory using spin-torque magnetic tunnel junctions and method for write state of the multi-layer magnetic random access memory | Mar 30, 2008 | Issued |
Array
(
[id] => 4844623
[patent_doc_number] => 20080181031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'Data strobe synchronization circuit and method for double data rate, multi-bit writes'
[patent_app_type] => utility
[patent_app_number] => 12/077878
[patent_app_country] => US
[patent_app_date] => 2008-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4470
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20080181031.pdf
[firstpage_image] =>[orig_patent_app_number] => 12077878
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/077878 | Data strobe synchronization circuit and method for double data rate, multi-bit writes | Mar 19, 2008 | Issued |
Array
(
[id] => 7546719
[patent_doc_number] => 08054696
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-11-08
[patent_title] => 'System and method to improve reliability in memory word line'
[patent_app_type] => utility
[patent_app_number] => 12/052334
[patent_app_country] => US
[patent_app_date] => 2008-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5368
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/054/08054696.pdf
[firstpage_image] =>[orig_patent_app_number] => 12052334
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/052334 | System and method to improve reliability in memory word line | Mar 19, 2008 | Issued |
Array
(
[id] => 4750960
[patent_doc_number] => 20080159031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'PARALLEL READ FOR FRONT END COMPRESSION MODE'
[patent_app_type] => utility
[patent_app_number] => 12/049110
[patent_app_country] => US
[patent_app_date] => 2008-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3228
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20080159031.pdf
[firstpage_image] =>[orig_patent_app_number] => 12049110
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/049110 | PARALLEL READ FOR FRONT END COMPRESSION MODE | Mar 13, 2008 | Abandoned |
Array
(
[id] => 367518
[patent_doc_number] => 07480203
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-20
[patent_title] => 'Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM'
[patent_app_type] => utility
[patent_app_number] => 12/072109
[patent_app_country] => US
[patent_app_date] => 2008-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 5158
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/480/07480203.pdf
[firstpage_image] =>[orig_patent_app_number] => 12072109
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/072109 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM | Feb 21, 2008 | Issued |
Array
(
[id] => 4871908
[patent_doc_number] => 20080198642
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-21
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/033372
[patent_app_country] => US
[patent_app_date] => 2008-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8499
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0198/20080198642.pdf
[firstpage_image] =>[orig_patent_app_number] => 12033372
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033372 | Semiconductor memory device | Feb 18, 2008 | Issued |
Array
(
[id] => 206317
[patent_doc_number] => 07630224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-08
[patent_title] => 'Semiconductor integrated circuit device and layout method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/033126
[patent_app_country] => US
[patent_app_date] => 2008-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 5958
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/630/07630224.pdf
[firstpage_image] =>[orig_patent_app_number] => 12033126
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033126 | Semiconductor integrated circuit device and layout method thereof | Feb 18, 2008 | Issued |
Array
(
[id] => 5390366
[patent_doc_number] => 20090207679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'Systems and Methods for Data Transfers Between Memory Cells'
[patent_app_type] => utility
[patent_app_number] => 12/033198
[patent_app_country] => US
[patent_app_date] => 2008-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7552
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0207/20090207679.pdf
[firstpage_image] =>[orig_patent_app_number] => 12033198
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033198 | Systems and methods for data transfers between memory cells | Feb 18, 2008 | Issued |
Array
(
[id] => 192038
[patent_doc_number] => 07643357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture'
[patent_app_type] => utility
[patent_app_number] => 12/032798
[patent_app_country] => US
[patent_app_date] => 2008-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3578
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/643/07643357.pdf
[firstpage_image] =>[orig_patent_app_number] => 12032798
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/032798 | System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture | Feb 17, 2008 | Issued |
Array
(
[id] => 5451216
[patent_doc_number] => 20090067252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-12
[patent_title] => 'FUSE DATA ACQUISITION'
[patent_app_type] => utility
[patent_app_number] => 12/032928
[patent_app_country] => US
[patent_app_date] => 2008-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7313
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20090067252.pdf
[firstpage_image] =>[orig_patent_app_number] => 12032928
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/032928 | Fuse data acquisition | Feb 17, 2008 | Issued |
Array
(
[id] => 4871942
[patent_doc_number] => 20080198676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-21
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH A CHANGEABLE SUBSTRATE POTENTIAL'
[patent_app_type] => utility
[patent_app_number] => 12/032336
[patent_app_country] => US
[patent_app_date] => 2008-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6736
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0198/20080198676.pdf
[firstpage_image] =>[orig_patent_app_number] => 12032336
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/032336 | Semiconductor memory device and method with a changeable substrate potential | Feb 14, 2008 | Issued |
Array
(
[id] => 187112
[patent_doc_number] => 07646646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/032206
[patent_app_country] => US
[patent_app_date] => 2008-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11277
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/646/07646646.pdf
[firstpage_image] =>[orig_patent_app_number] => 12032206
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/032206 | Nonvolatile semiconductor memory device | Feb 14, 2008 | Issued |
Array
(
[id] => 144164
[patent_doc_number] => 07688625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Circuit arrangement and method for operating a circuit arrangement'
[patent_app_type] => utility
[patent_app_number] => 12/032202
[patent_app_country] => US
[patent_app_date] => 2008-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 7809
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/688/07688625.pdf
[firstpage_image] =>[orig_patent_app_number] => 12032202
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/032202 | Circuit arrangement and method for operating a circuit arrangement | Feb 14, 2008 | Issued |
Array
(
[id] => 5519992
[patent_doc_number] => 20090027973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-29
[patent_title] => 'NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/032110
[patent_app_country] => US
[patent_app_date] => 2008-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12412
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20090027973.pdf
[firstpage_image] =>[orig_patent_app_number] => 12032110
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/032110 | Non-volatile semiconductor storage device | Feb 14, 2008 | Issued |
Array
(
[id] => 4763879
[patent_doc_number] => 20080175090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-24
[patent_title] => 'Memory device and method having programmable address configurations'
[patent_app_type] => utility
[patent_app_number] => 12/011961
[patent_app_country] => US
[patent_app_date] => 2008-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5791
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20080175090.pdf
[firstpage_image] =>[orig_patent_app_number] => 12011961
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/011961 | Memory device and method having programmable address configurations | Jan 28, 2008 | Issued |
Array
(
[id] => 7551918
[patent_doc_number] => 08064255
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Architecture of a nvDRAM array and its sense regime'
[patent_app_type] => utility
[patent_app_number] => 12/006226
[patent_app_country] => US
[patent_app_date] => 2007-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4552
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/064/08064255.pdf
[firstpage_image] =>[orig_patent_app_number] => 12006226
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/006226 | Architecture of a nvDRAM array and its sense regime | Dec 30, 2007 | Issued |
Array
(
[id] => 4738515
[patent_doc_number] => 20080232167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'Current controlled recall schema'
[patent_app_type] => utility
[patent_app_number] => 12/006228
[patent_app_country] => US
[patent_app_date] => 2007-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4098
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20080232167.pdf
[firstpage_image] =>[orig_patent_app_number] => 12006228
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/006228 | Current controlled recall schema | Dec 30, 2007 | Issued |
Array
(
[id] => 4717327
[patent_doc_number] => 20080239849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'Semiconductor memory device with reduced sense amplification time and operation method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/006166
[patent_app_country] => US
[patent_app_date] => 2007-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4800
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20080239849.pdf
[firstpage_image] =>[orig_patent_app_number] => 12006166
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/006166 | Semiconductor memory device with reduced sense amplification time and operation method thereof | Dec 30, 2007 | Issued |
Array
(
[id] => 46555
[patent_doc_number] => 07778098
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-17
[patent_title] => 'Dummy cell for memory circuits'
[patent_app_type] => utility
[patent_app_number] => 12/006224
[patent_app_country] => US
[patent_app_date] => 2007-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3099
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/778/07778098.pdf
[firstpage_image] =>[orig_patent_app_number] => 12006224
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/006224 | Dummy cell for memory circuits | Dec 30, 2007 | Issued |