Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7589376 [patent_doc_number] => 07663943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Semiconductor memory device and method for reading/writing data thereof' [patent_app_type] => utility [patent_app_number] => 12/005964 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4342 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663943.pdf [firstpage_image] =>[orig_patent_app_number] => 12005964 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/005964
Semiconductor memory device and method for reading/writing data thereof Dec 27, 2007 Issued
Array ( [id] => 125549 [patent_doc_number] => 07706191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Systems and methods to reduce interference between memory cells' [patent_app_type] => utility [patent_app_number] => 12/005994 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2952 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706191.pdf [firstpage_image] =>[orig_patent_app_number] => 12005994 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/005994
Systems and methods to reduce interference between memory cells Dec 27, 2007 Issued
Array ( [id] => 319737 [patent_doc_number] => 07522453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'Non-volatile memory with source-side column select' [patent_app_type] => utility [patent_app_number] => 11/961134 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2293 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/522/07522453.pdf [firstpage_image] =>[orig_patent_app_number] => 11961134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961134
Non-volatile memory with source-side column select Dec 19, 2007 Issued
Array ( [id] => 4571309 [patent_doc_number] => 07839697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/961184 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 38 [patent_no_of_words] => 9844 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/839/07839697.pdf [firstpage_image] =>[orig_patent_app_number] => 11961184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961184
Semiconductor memory device Dec 19, 2007 Issued
Array ( [id] => 271480 [patent_doc_number] => 07564719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Method of programming in a flash memory device' [patent_app_type] => utility [patent_app_number] => 11/962049 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3532 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564719.pdf [firstpage_image] =>[orig_patent_app_number] => 11962049 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962049
Method of programming in a flash memory device Dec 19, 2007 Issued
Array ( [id] => 279038 [patent_doc_number] => 07558120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Semiconductor integrated circuit device comprising MOS transistor having charge storage layer and method for testing semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/961172 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 10080 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558120.pdf [firstpage_image] =>[orig_patent_app_number] => 11961172 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961172
Semiconductor integrated circuit device comprising MOS transistor having charge storage layer and method for testing semiconductor memory device Dec 19, 2007 Issued
Array ( [id] => 179018 [patent_doc_number] => 07656729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Circuit and method for decoding column addresses in semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 11/961998 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3669 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/656/07656729.pdf [firstpage_image] =>[orig_patent_app_number] => 11961998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961998
Circuit and method for decoding column addresses in semiconductor memory apparatus Dec 19, 2007 Issued
Array ( [id] => 7594588 [patent_doc_number] => 07626875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'Multi-wordline test control circuit and controlling method thereof' [patent_app_type] => utility [patent_app_number] => 11/962026 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7207 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626875.pdf [firstpage_image] =>[orig_patent_app_number] => 11962026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962026
Multi-wordline test control circuit and controlling method thereof Dec 19, 2007 Issued
Array ( [id] => 4948214 [patent_doc_number] => 20080304340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'DATA I/O LINE CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/962046 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8473 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20080304340.pdf [firstpage_image] =>[orig_patent_app_number] => 11962046 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962046
Data I/O line control circuit and semiconductor integrated circuit having the same Dec 19, 2007 Issued
Array ( [id] => 300837 [patent_doc_number] => 07539044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-26 [patent_title] => 'Memory device with capacitor and diode' [patent_app_type] => utility [patent_app_number] => 11/961064 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539044.pdf [firstpage_image] =>[orig_patent_app_number] => 11961064 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961064
Memory device with capacitor and diode Dec 19, 2007 Issued
Array ( [id] => 297071 [patent_doc_number] => 07542348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-02 [patent_title] => 'NOR flash memory including bipolar segment read circuit' [patent_app_type] => utility [patent_app_number] => 11/960538 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 31 [patent_no_of_words] => 12886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/542/07542348.pdf [firstpage_image] =>[orig_patent_app_number] => 11960538 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960538
NOR flash memory including bipolar segment read circuit Dec 18, 2007 Issued
Array ( [id] => 4750977 [patent_doc_number] => 20080159048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING POWER SUPPLY WIRING NETWORK' [patent_app_type] => utility [patent_app_number] => 11/959646 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3611 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20080159048.pdf [firstpage_image] =>[orig_patent_app_number] => 11959646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959646
SEMICONDUCTOR MEMORY DEVICE HAVING POWER SUPPLY WIRING NETWORK Dec 18, 2007 Abandoned
Array ( [id] => 4750947 [patent_doc_number] => 20080159018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING INTERNAL VOLTAGE GENERATION CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/959600 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2986 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20080159018.pdf [firstpage_image] =>[orig_patent_app_number] => 11959600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959600
SEMICONDUCTOR MEMORY DEVICE HAVING INTERNAL VOLTAGE GENERATION CIRCUITS Dec 18, 2007 Abandoned
Array ( [id] => 5544365 [patent_doc_number] => 20090154242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'FLASH MEMORY WITH OPTIMIZED WRITE SECTOR SPARES' [patent_app_type] => utility [patent_app_number] => 11/958425 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20090154242.pdf [firstpage_image] =>[orig_patent_app_number] => 11958425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958425
Flash memory with optimized write sector spares Dec 17, 2007 Issued
Array ( [id] => 5544358 [patent_doc_number] => 20090154235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'REDUCED STATE QUADBIT' [patent_app_type] => utility [patent_app_number] => 11/958557 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20090154235.pdf [firstpage_image] =>[orig_patent_app_number] => 11958557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958557
Reduced state quadbit Dec 17, 2007 Issued
Array ( [id] => 153844 [patent_doc_number] => 07684257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Area efficient and fast static random access memory circuit and method' [patent_app_type] => utility [patent_app_number] => 11/958215 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5061 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/684/07684257.pdf [firstpage_image] =>[orig_patent_app_number] => 11958215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958215
Area efficient and fast static random access memory circuit and method Dec 16, 2007 Issued
Array ( [id] => 4750941 [patent_doc_number] => 20080159012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, AND MULTI-CHIP PACKAGE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/958377 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3502 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20080159012.pdf [firstpage_image] =>[orig_patent_app_number] => 11958377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958377
Semiconductor memory device, and multi-chip package and method of operating the same Dec 16, 2007 Issued
Array ( [id] => 240541 [patent_doc_number] => 07593263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Memory device with reduced reading latency' [patent_app_type] => utility [patent_app_number] => 11/958011 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7723 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/593/07593263.pdf [firstpage_image] =>[orig_patent_app_number] => 11958011 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958011
Memory device with reduced reading latency Dec 16, 2007 Issued
Array ( [id] => 5347715 [patent_doc_number] => 20090003076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'MEMORY DEVICE AND READING METHOD' [patent_app_type] => utility [patent_app_number] => 11/958375 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3678 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20090003076.pdf [firstpage_image] =>[orig_patent_app_number] => 11958375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958375
Memory device and reading method Dec 16, 2007 Issued
Array ( [id] => 144246 [patent_doc_number] => 07688667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Voltage converter circuit and flash memory device having the same' [patent_app_type] => utility [patent_app_number] => 11/958379 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4090 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/688/07688667.pdf [firstpage_image] =>[orig_patent_app_number] => 11958379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958379
Voltage converter circuit and flash memory device having the same Dec 16, 2007 Issued
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