Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5440334 [patent_doc_number] => 20090091973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/868042 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2900 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091973.pdf [firstpage_image] =>[orig_patent_app_number] => 11868042 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/868042
Reducing effects of program disturb in a memory device Oct 4, 2007 Issued
Array ( [id] => 5440324 [patent_doc_number] => 20090091963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/867208 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2482 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091963.pdf [firstpage_image] =>[orig_patent_app_number] => 11867208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867208
MEMORY DEVICE Oct 3, 2007 Abandoned
Array ( [id] => 6331515 [patent_doc_number] => 20100246237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'ANTI-FUSE ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/679278 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4319 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20100246237.pdf [firstpage_image] =>[orig_patent_app_number] => 12679278 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/679278
Anti-fuse element Oct 2, 2007 Issued
Array ( [id] => 5427238 [patent_doc_number] => 20090086548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 11/866018 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5753 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20090086548.pdf [firstpage_image] =>[orig_patent_app_number] => 11866018 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866018
FLASH MEMORY Oct 1, 2007 Abandoned
Array ( [id] => 5427224 [patent_doc_number] => 20090086534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES' [patent_app_type] => utility [patent_app_number] => 11/865134 [patent_app_country] => US [patent_app_date] => 2007-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4376 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20090086534.pdf [firstpage_image] =>[orig_patent_app_number] => 11865134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/865134
Apparatus and method for implementing precise sensing of PCRAM devices Sep 30, 2007 Issued
Array ( [id] => 7589054 [patent_doc_number] => 07663903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Semiconductor memory device having improved voltage transmission path and driving method thereof' [patent_app_type] => utility [patent_app_number] => 11/864604 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4474 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663903.pdf [firstpage_image] =>[orig_patent_app_number] => 11864604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864604
Semiconductor memory device having improved voltage transmission path and driving method thereof Sep 27, 2007 Issued
Array ( [id] => 4942918 [patent_doc_number] => 20080080243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/864089 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15676 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080243.pdf [firstpage_image] =>[orig_patent_app_number] => 11864089 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864089
Semiconductor memory device having different capacity areas Sep 27, 2007 Issued
Array ( [id] => 327688 [patent_doc_number] => 07515469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-07 [patent_title] => 'Column redundancy RAM for dynamic bit replacement in FLASH memory' [patent_app_type] => utility [patent_app_number] => 11/862436 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2486 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/515/07515469.pdf [firstpage_image] =>[orig_patent_app_number] => 11862436 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/862436
Column redundancy RAM for dynamic bit replacement in FLASH memory Sep 26, 2007 Issued
Array ( [id] => 124265 [patent_doc_number] => 07710789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Synchronous address and data multiplexed mode for SRAM' [patent_app_type] => utility [patent_app_number] => 11/863164 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8740 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/710/07710789.pdf [firstpage_image] =>[orig_patent_app_number] => 11863164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863164
Synchronous address and data multiplexed mode for SRAM Sep 26, 2007 Issued
Array ( [id] => 312079 [patent_doc_number] => 07529114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/861878 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529114.pdf [firstpage_image] =>[orig_patent_app_number] => 11861878 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861878
Semiconductor memory device Sep 25, 2007 Issued
Array ( [id] => 5507064 [patent_doc_number] => 20090080271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Memory Cell, Memory Device, Device and Method of Accessing a Memory Cell' [patent_app_type] => utility [patent_app_number] => 11/861286 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7254 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080271.pdf [firstpage_image] =>[orig_patent_app_number] => 11861286 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861286
Memory cell, memory device, device and method of accessing a memory cell Sep 25, 2007 Issued
Array ( [id] => 279069 [patent_doc_number] => 07558151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Methods and circuits for DDR-2 memory device read data resynchronization' [patent_app_type] => utility [patent_app_number] => 11/860910 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558151.pdf [firstpage_image] =>[orig_patent_app_number] => 11860910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/860910
Methods and circuits for DDR-2 memory device read data resynchronization Sep 24, 2007 Issued
Array ( [id] => 5507070 [patent_doc_number] => 20090080277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'MEMORY CELL FUSE CIRCUIT AND CONTROLLING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/860656 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1869 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080277.pdf [firstpage_image] =>[orig_patent_app_number] => 11860656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/860656
Memory cell fuse circuit and controlling method thereof Sep 24, 2007 Issued
Array ( [id] => 5507059 [patent_doc_number] => 20090080266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'DOUBLE DATA RATE (DDR) LOW POWER IDLE MODE THROUGH REFERENCE OFFSET' [patent_app_type] => utility [patent_app_number] => 11/861090 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080266.pdf [firstpage_image] =>[orig_patent_app_number] => 11861090 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861090
DOUBLE DATA RATE (DDR) LOW POWER IDLE MODE THROUGH REFERENCE OFFSET Sep 24, 2007 Abandoned
Array ( [id] => 222004 [patent_doc_number] => 07609551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/860956 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 79 [patent_no_of_words] => 28518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/609/07609551.pdf [firstpage_image] =>[orig_patent_app_number] => 11860956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/860956
Semiconductor memory device Sep 24, 2007 Issued
Array ( [id] => 5507041 [patent_doc_number] => 20090080248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'DATA STORAGE AND PROCESSING ALGORITHM FOR PLACEMENT OF MULTI - LEVEL FLASH CELL (MLC) VT' [patent_app_type] => utility [patent_app_number] => 11/861240 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1747 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080248.pdf [firstpage_image] =>[orig_patent_app_number] => 11861240 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861240
Data storage and processing algorithm for placement of multi-level flash cell (MLC) VT Sep 24, 2007 Issued
Array ( [id] => 4858108 [patent_doc_number] => 20080266958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 11/861102 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4925 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266958.pdf [firstpage_image] =>[orig_patent_app_number] => 11861102 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861102
Flash memory array of floating gate-based non-volatile memory cells Sep 24, 2007 Issued
Array ( [id] => 5507040 [patent_doc_number] => 20090080247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'USING MLC FLASH AS SLC BY WRITING DUMMY DATA' [patent_app_type] => utility [patent_app_number] => 11/861140 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080247.pdf [firstpage_image] =>[orig_patent_app_number] => 11861140 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861140
Using MLC flash as SLC by writing dummy data Sep 24, 2007 Issued
Array ( [id] => 331524 [patent_doc_number] => 07512024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'High-speed memory device easily testable by low-speed automatic test equipment and input/output pin control method thereof' [patent_app_type] => utility [patent_app_number] => 11/859824 [patent_app_country] => US [patent_app_date] => 2007-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512024.pdf [firstpage_image] =>[orig_patent_app_number] => 11859824 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/859824
High-speed memory device easily testable by low-speed automatic test equipment and input/output pin control method thereof Sep 23, 2007 Issued
Array ( [id] => 588432 [patent_doc_number] => 07457165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Non-volatile memory device and method of programming same' [patent_app_type] => utility [patent_app_number] => 11/855531 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/457/07457165.pdf [firstpage_image] =>[orig_patent_app_number] => 11855531 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/855531
Non-volatile memory device and method of programming same Sep 13, 2007 Issued
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