
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 367508
[patent_doc_number] => 07480193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-20
[patent_title] => 'Memory component with multiple delayed timing signals'
[patent_app_type] => utility
[patent_app_number] => 11/746007
[patent_app_country] => US
[patent_app_date] => 2007-05-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/480/07480193.pdf
[firstpage_image] =>[orig_patent_app_number] => 11746007
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/746007 | Memory component with multiple delayed timing signals | May 7, 2007 | Issued |
Array
(
[id] => 5246295
[patent_doc_number] => 20070242529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-18
[patent_title] => 'Method and Apparatus for Accessing Contents of Memory Cells'
[patent_app_type] => utility
[patent_app_number] => 11/745442
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[patent_app_date] => 2007-05-07
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[firstpage_image] =>[orig_patent_app_number] => 11745442
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/745442 | Method and apparatus for accessing contents of memory cells | May 6, 2007 | Issued |
Array
(
[id] => 596542
[patent_doc_number] => 07440316
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[patent_issue_date] => 2008-10-21
[patent_title] => '8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory'
[patent_app_type] => utility
[patent_app_number] => 11/741890
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[pdf_file] => patents/07/440/07440316.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741890 | 8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory | Apr 29, 2007 | Issued |
Array
(
[id] => 808417
[patent_doc_number] => 07420832
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-09-02
[patent_title] => 'Array split across three-dimensional interconnected chips'
[patent_app_type] => utility
[patent_app_number] => 11/741902
[patent_app_country] => US
[patent_app_date] => 2007-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/07/420/07420832.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741902
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741902 | Array split across three-dimensional interconnected chips | Apr 29, 2007 | Issued |
Array
(
[id] => 5009508
[patent_doc_number] => 20070279986
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[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/741936
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[patent_app_date] => 2007-04-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0279/20070279986.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741936
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741936 | Nonvolatile semiconductor memory | Apr 29, 2007 | Issued |
Array
(
[id] => 4858076
[patent_doc_number] => 20080266926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES'
[patent_app_type] => utility
[patent_app_number] => 11/741996
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[firstpage_image] =>[orig_patent_app_number] => 11741996
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741996 | Transfer of non-associated information on flash memory devices | Apr 29, 2007 | Issued |
Array
(
[id] => 271471
[patent_doc_number] => 07564710
[patent_country] => US
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[patent_issue_date] => 2009-07-21
[patent_title] => 'Circuit for programming a memory element'
[patent_app_type] => utility
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[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/564/07564710.pdf
[firstpage_image] =>[orig_patent_app_number] => 11742090
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/742090 | Circuit for programming a memory element | Apr 29, 2007 | Issued |
Array
(
[id] => 4858079
[patent_doc_number] => 20080266929
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY'
[patent_app_type] => utility
[patent_app_number] => 11/741462
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0266/20080266929.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741462
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741462 | Reference cell layout with enhanced RTN immunity | Apr 26, 2007 | Issued |
Array
(
[id] => 594713
[patent_doc_number] => 07443759
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-10-28
[patent_title] => 'Reduced-power memory with per-sector ground control'
[patent_app_type] => utility
[patent_app_number] => 11/740892
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[patent_app_date] => 2007-04-26
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[pdf_file] => patents/07/443/07443759.pdf
[firstpage_image] =>[orig_patent_app_number] => 11740892
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740892 | Reduced-power memory with per-sector ground control | Apr 25, 2007 | Issued |
Array
(
[id] => 5223998
[patent_doc_number] => 20070253264
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[patent_issue_date] => 2007-11-01
[patent_title] => 'Integrated Semiconductor Memory with a Test Function and Method for Testing an Integrated Semiconductor Memory'
[patent_app_type] => utility
[patent_app_number] => 11/740768
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740768 | Integrated Semiconductor Memory with a Test Function and Method for Testing an Integrated Semiconductor Memory | Apr 25, 2007 | Abandoned |
Array
(
[id] => 7590402
[patent_doc_number] => 07663961
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[patent_title] => 'Reduced-power memory with per-sector power/ground control and early address'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740901 | Reduced-power memory with per-sector power/ground control and early address | Apr 25, 2007 | Issued |
Array
(
[id] => 5223974
[patent_doc_number] => 20070253240
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[patent_issue_date] => 2007-11-01
[patent_title] => 'FAULT TOLERANT ASYNCHRONOUS CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 11/740168
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[firstpage_image] =>[orig_patent_app_number] => 11740168
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740168 | Fault tolerant asynchronous circuits | Apr 24, 2007 | Issued |
Array
(
[id] => 596611
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[patent_title] => 'Non-volatile storage with reduced power consumption during read operations'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/740096 | Non-volatile storage with reduced power consumption during read operations | Apr 24, 2007 | Issued |
Array
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[id] => 5111676
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[patent_title] => 'Layout method of a semiconductor memory device'
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Array
(
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Array
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/704951 | Semiconductor memory device | Feb 11, 2007 | Issued |