Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 367508 [patent_doc_number] => 07480193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Memory component with multiple delayed timing signals' [patent_app_type] => utility [patent_app_number] => 11/746007 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480193.pdf [firstpage_image] =>[orig_patent_app_number] => 11746007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/746007
Memory component with multiple delayed timing signals May 7, 2007 Issued
Array ( [id] => 5246295 [patent_doc_number] => 20070242529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Method and Apparatus for Accessing Contents of Memory Cells' [patent_app_type] => utility [patent_app_number] => 11/745442 [patent_app_country] => US [patent_app_date] => 2007-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5341 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242529.pdf [firstpage_image] =>[orig_patent_app_number] => 11745442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/745442
Method and apparatus for accessing contents of memory cells May 6, 2007 Issued
Array ( [id] => 596542 [patent_doc_number] => 07440316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-21 [patent_title] => '8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory' [patent_app_type] => utility [patent_app_number] => 11/741890 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/440/07440316.pdf [firstpage_image] =>[orig_patent_app_number] => 11741890 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741890
8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory Apr 29, 2007 Issued
Array ( [id] => 808417 [patent_doc_number] => 07420832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-02 [patent_title] => 'Array split across three-dimensional interconnected chips' [patent_app_type] => utility [patent_app_number] => 11/741902 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6008 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/420/07420832.pdf [firstpage_image] =>[orig_patent_app_number] => 11741902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741902
Array split across three-dimensional interconnected chips Apr 29, 2007 Issued
Array ( [id] => 5009508 [patent_doc_number] => 20070279986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 11/741936 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 23044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20070279986.pdf [firstpage_image] =>[orig_patent_app_number] => 11741936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741936
Nonvolatile semiconductor memory Apr 29, 2007 Issued
Array ( [id] => 4858076 [patent_doc_number] => 20080266926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 11/741996 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6815 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266926.pdf [firstpage_image] =>[orig_patent_app_number] => 11741996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741996
Transfer of non-associated information on flash memory devices Apr 29, 2007 Issued
Array ( [id] => 271471 [patent_doc_number] => 07564710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Circuit for programming a memory element' [patent_app_type] => utility [patent_app_number] => 11/742090 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 11648 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564710.pdf [firstpage_image] =>[orig_patent_app_number] => 11742090 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/742090
Circuit for programming a memory element Apr 29, 2007 Issued
Array ( [id] => 4858079 [patent_doc_number] => 20080266929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'REFERENCE CELL LAYOUT WITH ENHANCED RTN IMMUNITY' [patent_app_type] => utility [patent_app_number] => 11/741462 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1902 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266929.pdf [firstpage_image] =>[orig_patent_app_number] => 11741462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741462
Reference cell layout with enhanced RTN immunity Apr 26, 2007 Issued
Array ( [id] => 594713 [patent_doc_number] => 07443759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-28 [patent_title] => 'Reduced-power memory with per-sector ground control' [patent_app_type] => utility [patent_app_number] => 11/740892 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 13889 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443759.pdf [firstpage_image] =>[orig_patent_app_number] => 11740892 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740892
Reduced-power memory with per-sector ground control Apr 25, 2007 Issued
Array ( [id] => 5223998 [patent_doc_number] => 20070253264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Integrated Semiconductor Memory with a Test Function and Method for Testing an Integrated Semiconductor Memory' [patent_app_type] => utility [patent_app_number] => 11/740768 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6543 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253264.pdf [firstpage_image] =>[orig_patent_app_number] => 11740768 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740768
Integrated Semiconductor Memory with a Test Function and Method for Testing an Integrated Semiconductor Memory Apr 25, 2007 Abandoned
Array ( [id] => 7590402 [patent_doc_number] => 07663961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-16 [patent_title] => 'Reduced-power memory with per-sector power/ground control and early address' [patent_app_type] => utility [patent_app_number] => 11/740901 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 13835 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663961.pdf [firstpage_image] =>[orig_patent_app_number] => 11740901 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740901
Reduced-power memory with per-sector power/ground control and early address Apr 25, 2007 Issued
Array ( [id] => 5223974 [patent_doc_number] => 20070253240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'FAULT TOLERANT ASYNCHRONOUS CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/740168 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5913 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253240.pdf [firstpage_image] =>[orig_patent_app_number] => 11740168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740168
Fault tolerant asynchronous circuits Apr 24, 2007 Issued
Array ( [id] => 596611 [patent_doc_number] => 07440327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-21 [patent_title] => 'Non-volatile storage with reduced power consumption during read operations' [patent_app_type] => utility [patent_app_number] => 11/740096 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 15672 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/440/07440327.pdf [firstpage_image] =>[orig_patent_app_number] => 11740096 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740096
Non-volatile storage with reduced power consumption during read operations Apr 24, 2007 Issued
Array ( [id] => 5111676 [patent_doc_number] => 20070195591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Layout method of a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/790444 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3945 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195591.pdf [firstpage_image] =>[orig_patent_app_number] => 11790444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790444
Layout method of a semiconductor memory device Apr 24, 2007 Issued
Array ( [id] => 5111657 [patent_doc_number] => 20070195572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => '276-PIN BUFFERED MEMORY MODULE WITH ENHANCED FAULT TOLERANCE' [patent_app_type] => utility [patent_app_number] => 11/735640 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195572.pdf [firstpage_image] =>[orig_patent_app_number] => 11735640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/735640
276-pin buffered memory module with enhanced fault tolerance Apr 15, 2007 Issued
Array ( [id] => 312077 [patent_doc_number] => 07529112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => '276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment' [patent_app_type] => utility [patent_app_number] => 11/695679 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 11630 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529112.pdf [firstpage_image] =>[orig_patent_app_number] => 11695679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/695679
276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment Apr 2, 2007 Issued
Array ( [id] => 364847 [patent_doc_number] => 07483308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Programming and erasing method for charge-trapping memory devices' [patent_app_type] => utility [patent_app_number] => 11/685623 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3019 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/483/07483308.pdf [firstpage_image] =>[orig_patent_app_number] => 11685623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685623
Programming and erasing method for charge-trapping memory devices Mar 12, 2007 Issued
Array ( [id] => 5111705 [patent_doc_number] => 20070195620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/714766 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8609 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195620.pdf [firstpage_image] =>[orig_patent_app_number] => 11714766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714766
Semiconductor memory Mar 6, 2007 Issued
Array ( [id] => 4987257 [patent_doc_number] => 20070153595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Apparatus and method for repairing a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/714979 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5054 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153595.pdf [firstpage_image] =>[orig_patent_app_number] => 11714979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714979
Apparatus and method for repairing a semiconductor memory Mar 6, 2007 Issued
Array ( [id] => 594677 [patent_doc_number] => 07443754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/704951 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443754.pdf [firstpage_image] =>[orig_patent_app_number] => 11704951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704951
Semiconductor memory device Feb 11, 2007 Issued
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