Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5111676 [patent_doc_number] => 20070195591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Layout method of a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/790444 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3945 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195591.pdf [firstpage_image] =>[orig_patent_app_number] => 11790444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790444
Layout method of a semiconductor memory device Apr 24, 2007 Issued
Array ( [id] => 5223974 [patent_doc_number] => 20070253240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'FAULT TOLERANT ASYNCHRONOUS CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/740168 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5913 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253240.pdf [firstpage_image] =>[orig_patent_app_number] => 11740168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740168
Fault tolerant asynchronous circuits Apr 24, 2007 Issued
Array ( [id] => 5111657 [patent_doc_number] => 20070195572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => '276-PIN BUFFERED MEMORY MODULE WITH ENHANCED FAULT TOLERANCE' [patent_app_type] => utility [patent_app_number] => 11/735640 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195572.pdf [firstpage_image] =>[orig_patent_app_number] => 11735640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/735640
276-pin buffered memory module with enhanced fault tolerance Apr 15, 2007 Issued
Array ( [id] => 312077 [patent_doc_number] => 07529112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => '276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment' [patent_app_type] => utility [patent_app_number] => 11/695679 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 11630 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529112.pdf [firstpage_image] =>[orig_patent_app_number] => 11695679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/695679
276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment Apr 2, 2007 Issued
Array ( [id] => 364847 [patent_doc_number] => 07483308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Programming and erasing method for charge-trapping memory devices' [patent_app_type] => utility [patent_app_number] => 11/685623 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3019 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/483/07483308.pdf [firstpage_image] =>[orig_patent_app_number] => 11685623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685623
Programming and erasing method for charge-trapping memory devices Mar 12, 2007 Issued
Array ( [id] => 4987257 [patent_doc_number] => 20070153595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Apparatus and method for repairing a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/714979 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5054 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153595.pdf [firstpage_image] =>[orig_patent_app_number] => 11714979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714979
Apparatus and method for repairing a semiconductor memory Mar 6, 2007 Issued
Array ( [id] => 5111705 [patent_doc_number] => 20070195620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/714766 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8609 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195620.pdf [firstpage_image] =>[orig_patent_app_number] => 11714766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714766
Semiconductor memory Mar 6, 2007 Issued
Array ( [id] => 594677 [patent_doc_number] => 07443754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/704951 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443754.pdf [firstpage_image] =>[orig_patent_app_number] => 11704951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704951
Semiconductor memory device Feb 11, 2007 Issued
Array ( [id] => 4953601 [patent_doc_number] => 20080186625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Data Storage Medium and Method for Accessing Digital Data Therein' [patent_app_type] => utility [patent_app_number] => 11/672216 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4754 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20080186625.pdf [firstpage_image] =>[orig_patent_app_number] => 11672216 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/672216
Data storage medium and method for accessing digital data therein Feb 6, 2007 Issued
Array ( [id] => 4953762 [patent_doc_number] => 20080186786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'FAST AND ACCURATE SENSING AMPLIFIER FOR LOW VOLTAGE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 11/670626 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4467 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20080186786.pdf [firstpage_image] =>[orig_patent_app_number] => 11670626 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670626
Fast and accurate sensing amplifier for low voltage semiconductor memory Feb 1, 2007 Issued
Array ( [id] => 5099952 [patent_doc_number] => 20070183213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/701404 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17174 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183213.pdf [firstpage_image] =>[orig_patent_app_number] => 11701404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701404
Nonvolatile semiconductor memory device Feb 1, 2007 Issued
Array ( [id] => 804684 [patent_doc_number] => 07423901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Calibration system for writing and reading multiple states into phase change memory' [patent_app_type] => utility [patent_app_number] => 11/701338 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7618 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/423/07423901.pdf [firstpage_image] =>[orig_patent_app_number] => 11701338 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701338
Calibration system for writing and reading multiple states into phase change memory Jan 31, 2007 Issued
Array ( [id] => 5099949 [patent_doc_number] => 20070183210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Program method of flash memory capable of compensating read margin reduced due to charge loss' [patent_app_type] => utility [patent_app_number] => 11/700834 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3970 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183210.pdf [firstpage_image] =>[orig_patent_app_number] => 11700834 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700834
Program method of flash memory capable of compensating read margin reduced due to charge loss Jan 31, 2007 Issued
Array ( [id] => 834816 [patent_doc_number] => 07397705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-08 [patent_title] => 'Method for programming multi-level cell memory array' [patent_app_type] => utility [patent_app_number] => 11/670382 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 8182 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397705.pdf [firstpage_image] =>[orig_patent_app_number] => 11670382 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670382
Method for programming multi-level cell memory array Jan 31, 2007 Issued
Array ( [id] => 4956456 [patent_doc_number] => 20080189480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Memory configured on a common substrate' [patent_app_type] => utility [patent_app_number] => 11/701006 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2369 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189480.pdf [firstpage_image] =>[orig_patent_app_number] => 11701006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701006
Memory configured on a common substrate Jan 31, 2007 Issued
Array ( [id] => 4844635 [patent_doc_number] => 20080181043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Configurable device ID in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/701302 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2645 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20080181043.pdf [firstpage_image] =>[orig_patent_app_number] => 11701302 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701302
Configurable device ID in non-volatile memory Jan 30, 2007 Issued
Array ( [id] => 834835 [patent_doc_number] => 07397710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same' [patent_app_type] => utility [patent_app_number] => 11/700417 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 21935 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397710.pdf [firstpage_image] =>[orig_patent_app_number] => 11700417 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700417
Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same Jan 30, 2007 Issued
Array ( [id] => 5099961 [patent_doc_number] => 20070183222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/700186 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4787 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183222.pdf [firstpage_image] =>[orig_patent_app_number] => 11700186 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700186
Semiconductor memory device Jan 30, 2007 Issued
Array ( [id] => 818375 [patent_doc_number] => 07411838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/700184 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 6280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/411/07411838.pdf [firstpage_image] =>[orig_patent_app_number] => 11700184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700184
Semiconductor memory device Jan 30, 2007 Issued
Array ( [id] => 850453 [patent_doc_number] => 07382670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-03 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/669420 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7979 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/382/07382670.pdf [firstpage_image] =>[orig_patent_app_number] => 11669420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669420
Semiconductor integrated circuit device Jan 30, 2007 Issued
Menu