Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 572077 [patent_doc_number] => 07471540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Non-volatile semiconductor memory based on enhanced gate oxide breakdown' [patent_app_type] => utility [patent_app_number] => 11/657982 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3362 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/471/07471540.pdf [firstpage_image] =>[orig_patent_app_number] => 11657982 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657982
Non-volatile semiconductor memory based on enhanced gate oxide breakdown Jan 23, 2007 Issued
Array ( [id] => 5187148 [patent_doc_number] => 20070165456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'System and method for purge of flash memory' [patent_app_type] => utility [patent_app_number] => 11/654317 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165456.pdf [firstpage_image] =>[orig_patent_app_number] => 11654317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654317
System and method for purge of flash memory Jan 16, 2007 Abandoned
Array ( [id] => 36139 [patent_doc_number] => 07787321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'High performance sense amplifier and method thereof for memory system' [patent_app_type] => utility [patent_app_number] => 11/623894 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/787/07787321.pdf [firstpage_image] =>[orig_patent_app_number] => 11623894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/623894
High performance sense amplifier and method thereof for memory system Jan 16, 2007 Issued
Array ( [id] => 4969888 [patent_doc_number] => 20070109890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Memory, processing system and methods for use therewith' [patent_app_type] => utility [patent_app_number] => 11/652327 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3842 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109890.pdf [firstpage_image] =>[orig_patent_app_number] => 11652327 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652327
Memory, processing system and methods for use therewith Jan 10, 2007 Issued
Array ( [id] => 838475 [patent_doc_number] => 07394699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Sense amplifier for a non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 11/651687 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2929 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394699.pdf [firstpage_image] =>[orig_patent_app_number] => 11651687 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651687
Sense amplifier for a non-volatile memory device Jan 9, 2007 Issued
Array ( [id] => 5021178 [patent_doc_number] => 20070147144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 11/616112 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 22291 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20070147144.pdf [firstpage_image] =>[orig_patent_app_number] => 11616112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616112
Semiconductor integrated circuit device Dec 25, 2006 Issued
Array ( [id] => 4878267 [patent_doc_number] => 20080151650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'METHOD OF REDUCING WORDLINE RECOVERY TIME' [patent_app_type] => utility [patent_app_number] => 11/615868 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2863 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151650.pdf [firstpage_image] =>[orig_patent_app_number] => 11615868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615868
Method of reducing wordline recovery time Dec 21, 2006 Issued
Array ( [id] => 594661 [patent_doc_number] => 07443751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Programmable sense amplifier multiplexer circuit with dynamic latching mode' [patent_app_type] => utility [patent_app_number] => 11/615118 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8082 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443751.pdf [firstpage_image] =>[orig_patent_app_number] => 11615118 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615118
Programmable sense amplifier multiplexer circuit with dynamic latching mode Dec 21, 2006 Issued
Array ( [id] => 581646 [patent_doc_number] => 07463525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Negative wordline bias for reduction of leakage current during flash memory operation' [patent_app_type] => utility [patent_app_number] => 11/615280 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6279 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463525.pdf [firstpage_image] =>[orig_patent_app_number] => 11615280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615280
Negative wordline bias for reduction of leakage current during flash memory operation Dec 21, 2006 Issued
Array ( [id] => 4878290 [patent_doc_number] => 20080151673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'PG-Gated Data Retention Technique for Reducing Leakage in Memory Cells' [patent_app_type] => utility [patent_app_number] => 11/615422 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5653 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151673.pdf [firstpage_image] =>[orig_patent_app_number] => 11615422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615422
PG-gated data retention technique for reducing leakage in memory cells Dec 21, 2006 Issued
Array ( [id] => 4878253 [patent_doc_number] => 20080151636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'REPETITIVE ERASE VERIFY TECHNIQUE FOR FLASH MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 11/615710 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6271 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151636.pdf [firstpage_image] =>[orig_patent_app_number] => 11615710 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615710
Repetitive erase verify technique for flash memory devices Dec 21, 2006 Issued
Array ( [id] => 844874 [patent_doc_number] => 07388776 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-17 [patent_title] => 'Three-dimensional magnetic memory' [patent_app_type] => utility [patent_app_number] => 11/615618 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 11639 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/388/07388776.pdf [firstpage_image] =>[orig_patent_app_number] => 11615618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615618
Three-dimensional magnetic memory Dec 21, 2006 Issued
Array ( [id] => 5197909 [patent_doc_number] => 20070297227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Multi-Level Cell Memory Structures with Enlarged Second Bit Operation Window' [patent_app_type] => utility [patent_app_number] => 11/614916 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12284 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20070297227.pdf [firstpage_image] =>[orig_patent_app_number] => 11614916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614916
Multi-level cell memory structures with enlarged second bit operation window Dec 20, 2006 Issued
Array ( [id] => 5192894 [patent_doc_number] => 20070081376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Memory module and memory system' [patent_app_type] => utility [patent_app_number] => 11/634405 [patent_app_country] => US [patent_app_date] => 2006-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11238 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20070081376.pdf [firstpage_image] =>[orig_patent_app_number] => 11634405 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/634405
Memory module and memory system Dec 5, 2006 Issued
Array ( [id] => 154429 [patent_doc_number] => 07679952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Electronic circuit with a memory matrix' [patent_app_type] => utility [patent_app_number] => 12/096226 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4460 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/679/07679952.pdf [firstpage_image] =>[orig_patent_app_number] => 12096226 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/096226
Electronic circuit with a memory matrix Dec 3, 2006 Issued
Array ( [id] => 5158679 [patent_doc_number] => 20070171723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'NOR flash memory and related read method' [patent_app_type] => utility [patent_app_number] => 11/606029 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2589 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20070171723.pdf [firstpage_image] =>[orig_patent_app_number] => 11606029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/606029
NOR flash memory and related read method Nov 29, 2006 Issued
Array ( [id] => 4892031 [patent_doc_number] => 20080101128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Nonvolatile memory device and method of reading information from the same' [patent_app_type] => utility [patent_app_number] => 11/605225 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3187 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20080101128.pdf [firstpage_image] =>[orig_patent_app_number] => 11605225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605225
Nonvolatile memory device and method of reading information from the same Nov 28, 2006 Issued
Array ( [id] => 815027 [patent_doc_number] => 07414890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Semiconductor device including a high voltage generation circuit and method of a generating high voltage' [patent_app_type] => utility [patent_app_number] => 11/605227 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5772 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414890.pdf [firstpage_image] =>[orig_patent_app_number] => 11605227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605227
Semiconductor device including a high voltage generation circuit and method of a generating high voltage Nov 28, 2006 Issued
Array ( [id] => 838494 [patent_doc_number] => 07394710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Auto-recovery fault tolerant memory synchronization' [patent_app_type] => utility [patent_app_number] => 11/604719 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5032 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394710.pdf [firstpage_image] =>[orig_patent_app_number] => 11604719 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/604719
Auto-recovery fault tolerant memory synchronization Nov 27, 2006 Issued
Array ( [id] => 7596665 [patent_doc_number] => 07619917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Memory cell with trigger element' [patent_app_type] => utility [patent_app_number] => 11/605079 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4511 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619917.pdf [firstpage_image] =>[orig_patent_app_number] => 11605079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605079
Memory cell with trigger element Nov 27, 2006 Issued
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