Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 364853 [patent_doc_number] => 07483313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Dual ported memory with selective read and write protection' [patent_app_type] => utility [patent_app_number] => 11/669792 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2990 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/483/07483313.pdf [firstpage_image] =>[orig_patent_app_number] => 11669792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669792
Dual ported memory with selective read and write protection Jan 30, 2007 Issued
Array ( [id] => 4844638 [patent_doc_number] => 20080181046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 11/668844 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7905 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20080181046.pdf [firstpage_image] =>[orig_patent_app_number] => 11668844 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668844
Clock circuitry for DDR-SDRAM memory controller Jan 29, 2007 Issued
Array ( [id] => 300830 [patent_doc_number] => 07539036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Semiconductor memory device including plurality of memory mats' [patent_app_type] => utility [patent_app_number] => 11/699386 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5933 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539036.pdf [firstpage_image] =>[orig_patent_app_number] => 11699386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699386
Semiconductor memory device including plurality of memory mats Jan 29, 2007 Issued
Array ( [id] => 4690072 [patent_doc_number] => 20080034253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'FERROELECTRIC MEMORY WITH SPARE MEMORY CELL ARRAY AND ECC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/668706 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6560 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034253.pdf [firstpage_image] =>[orig_patent_app_number] => 11668706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668706
Ferroelectric memory with spare memory cell array and ECC circuit Jan 29, 2007 Issued
Array ( [id] => 4806880 [patent_doc_number] => 20080170458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'APPARATUS AND METHOD FOR REDUCING LEAKAGE CURRENTS OF INTEGRATED CIRCUITS HAVING AT LEAST ONE TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/668214 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4731 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20080170458.pdf [firstpage_image] =>[orig_patent_app_number] => 11668214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668214
Apparatus and method for reducing leakage currents of integrated circuits having at least one transistor Jan 28, 2007 Issued
Array ( [id] => 5118285 [patent_doc_number] => 20070139999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Magnetic memory device' [patent_app_type] => utility [patent_app_number] => 11/698872 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6437 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20070139999.pdf [firstpage_image] =>[orig_patent_app_number] => 11698872 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698872
Magnetic memory device Jan 28, 2007 Issued
Array ( [id] => 5251805 [patent_doc_number] => 20070133261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 11/698880 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4937 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133261.pdf [firstpage_image] =>[orig_patent_app_number] => 11698880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698880
Semiconductor storage device Jan 28, 2007 Abandoned
Array ( [id] => 5099920 [patent_doc_number] => 20070183181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Electrically programmable fuse bit' [patent_app_type] => utility [patent_app_number] => 11/699916 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4607 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183181.pdf [firstpage_image] =>[orig_patent_app_number] => 11699916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699916
Electrically programmable fuse bit Jan 28, 2007 Issued
Array ( [id] => 572077 [patent_doc_number] => 07471540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Non-volatile semiconductor memory based on enhanced gate oxide breakdown' [patent_app_type] => utility [patent_app_number] => 11/657982 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3362 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/471/07471540.pdf [firstpage_image] =>[orig_patent_app_number] => 11657982 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657982
Non-volatile semiconductor memory based on enhanced gate oxide breakdown Jan 23, 2007 Issued
Array ( [id] => 36139 [patent_doc_number] => 07787321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'High performance sense amplifier and method thereof for memory system' [patent_app_type] => utility [patent_app_number] => 11/623894 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/787/07787321.pdf [firstpage_image] =>[orig_patent_app_number] => 11623894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/623894
High performance sense amplifier and method thereof for memory system Jan 16, 2007 Issued
Array ( [id] => 5187148 [patent_doc_number] => 20070165456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'System and method for purge of flash memory' [patent_app_type] => utility [patent_app_number] => 11/654317 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165456.pdf [firstpage_image] =>[orig_patent_app_number] => 11654317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654317
System and method for purge of flash memory Jan 16, 2007 Abandoned
Array ( [id] => 4969888 [patent_doc_number] => 20070109890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Memory, processing system and methods for use therewith' [patent_app_type] => utility [patent_app_number] => 11/652327 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3842 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109890.pdf [firstpage_image] =>[orig_patent_app_number] => 11652327 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652327
Memory, processing system and methods for use therewith Jan 10, 2007 Issued
Array ( [id] => 838475 [patent_doc_number] => 07394699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Sense amplifier for a non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 11/651687 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2929 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394699.pdf [firstpage_image] =>[orig_patent_app_number] => 11651687 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651687
Sense amplifier for a non-volatile memory device Jan 9, 2007 Issued
Array ( [id] => 5021178 [patent_doc_number] => 20070147144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 11/616112 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 22291 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20070147144.pdf [firstpage_image] =>[orig_patent_app_number] => 11616112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616112
Semiconductor integrated circuit device Dec 25, 2006 Issued
Array ( [id] => 4878253 [patent_doc_number] => 20080151636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'REPETITIVE ERASE VERIFY TECHNIQUE FOR FLASH MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 11/615710 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6271 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151636.pdf [firstpage_image] =>[orig_patent_app_number] => 11615710 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615710
Repetitive erase verify technique for flash memory devices Dec 21, 2006 Issued
Array ( [id] => 581646 [patent_doc_number] => 07463525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Negative wordline bias for reduction of leakage current during flash memory operation' [patent_app_type] => utility [patent_app_number] => 11/615280 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6279 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463525.pdf [firstpage_image] =>[orig_patent_app_number] => 11615280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615280
Negative wordline bias for reduction of leakage current during flash memory operation Dec 21, 2006 Issued
Array ( [id] => 4878267 [patent_doc_number] => 20080151650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'METHOD OF REDUCING WORDLINE RECOVERY TIME' [patent_app_type] => utility [patent_app_number] => 11/615868 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2863 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151650.pdf [firstpage_image] =>[orig_patent_app_number] => 11615868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615868
Method of reducing wordline recovery time Dec 21, 2006 Issued
Array ( [id] => 594661 [patent_doc_number] => 07443751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Programmable sense amplifier multiplexer circuit with dynamic latching mode' [patent_app_type] => utility [patent_app_number] => 11/615118 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8082 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443751.pdf [firstpage_image] =>[orig_patent_app_number] => 11615118 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615118
Programmable sense amplifier multiplexer circuit with dynamic latching mode Dec 21, 2006 Issued
Array ( [id] => 844874 [patent_doc_number] => 07388776 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-17 [patent_title] => 'Three-dimensional magnetic memory' [patent_app_type] => utility [patent_app_number] => 11/615618 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 11639 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/388/07388776.pdf [firstpage_image] =>[orig_patent_app_number] => 11615618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615618
Three-dimensional magnetic memory Dec 21, 2006 Issued
Array ( [id] => 4878290 [patent_doc_number] => 20080151673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'PG-Gated Data Retention Technique for Reducing Leakage in Memory Cells' [patent_app_type] => utility [patent_app_number] => 11/615422 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5653 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151673.pdf [firstpage_image] =>[orig_patent_app_number] => 11615422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615422
PG-gated data retention technique for reducing leakage in memory cells Dec 21, 2006 Issued
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