
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 572077
[patent_doc_number] => 07471540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-30
[patent_title] => 'Non-volatile semiconductor memory based on enhanced gate oxide breakdown'
[patent_app_type] => utility
[patent_app_number] => 11/657982
[patent_app_country] => US
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Array
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[patent_issue_date] => 2007-07-19
[patent_title] => 'System and method for purge of flash memory'
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Array
(
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[patent_issue_date] => 2010-08-31
[patent_title] => 'High performance sense amplifier and method thereof for memory system'
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Array
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[patent_issue_date] => 2007-05-17
[patent_title] => 'Memory, processing system and methods for use therewith'
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Array
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[patent_title] => 'Sense amplifier for a non-volatile memory device'
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Array
(
[id] => 5021178
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[patent_issue_date] => 2007-06-28
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
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Array
(
[id] => 4878267
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[patent_title] => 'METHOD OF REDUCING WORDLINE RECOVERY TIME'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11615868
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615868 | Method of reducing wordline recovery time | Dec 21, 2006 | Issued |
Array
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[id] => 594661
[patent_doc_number] => 07443751
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[patent_issue_date] => 2008-10-28
[patent_title] => 'Programmable sense amplifier multiplexer circuit with dynamic latching mode'
[patent_app_type] => utility
[patent_app_number] => 11/615118
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615118 | Programmable sense amplifier multiplexer circuit with dynamic latching mode | Dec 21, 2006 | Issued |
Array
(
[id] => 581646
[patent_doc_number] => 07463525
[patent_country] => US
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[patent_issue_date] => 2008-12-09
[patent_title] => 'Negative wordline bias for reduction of leakage current during flash memory operation'
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Array
(
[id] => 4878290
[patent_doc_number] => 20080151673
[patent_country] => US
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[patent_issue_date] => 2008-06-26
[patent_title] => 'PG-Gated Data Retention Technique for Reducing Leakage in Memory Cells'
[patent_app_type] => utility
[patent_app_number] => 11/615422
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Array
(
[id] => 4878253
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[patent_title] => 'REPETITIVE ERASE VERIFY TECHNIQUE FOR FLASH MEMORY DEVICES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615710 | Repetitive erase verify technique for flash memory devices | Dec 21, 2006 | Issued |
Array
(
[id] => 844874
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Array
(
[id] => 5197909
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[patent_title] => 'Multi-Level Cell Memory Structures with Enlarged Second Bit Operation Window'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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