Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5116810 [patent_doc_number] => 20070138524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Semiconductor memory device and methods thereof' [patent_app_type] => utility [patent_app_number] => 11/604823 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4097 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138524.pdf [firstpage_image] =>[orig_patent_app_number] => 11604823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/604823
Semiconductor memory device and methods thereof Nov 27, 2006 Issued
Array ( [id] => 346153 [patent_doc_number] => 07499345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Non-volatile memory implemented with low-voltages transistors and related system and method' [patent_app_type] => utility [patent_app_number] => 11/605209 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5261 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499345.pdf [firstpage_image] =>[orig_patent_app_number] => 11605209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605209
Non-volatile memory implemented with low-voltages transistors and related system and method Nov 26, 2006 Issued
Array ( [id] => 4744540 [patent_doc_number] => 20080089142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Voltage generation circuit, flash memory device including the same and method for programming the flash memory device' [patent_app_type] => utility [patent_app_number] => 11/604227 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6168 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20080089142.pdf [firstpage_image] =>[orig_patent_app_number] => 11604227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/604227
Voltage generation circuit, flash memory device including the same and method for programming the flash memory device Nov 26, 2006 Issued
Array ( [id] => 5105623 [patent_doc_number] => 20070064498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Flash memory devices including multiple dummy cell array regions' [patent_app_type] => utility [patent_app_number] => 11/602645 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7600 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20070064498.pdf [firstpage_image] =>[orig_patent_app_number] => 11602645 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/602645
Flash memory devices including multiple dummy cell array regions Nov 20, 2006 Issued
Array ( [id] => 422671 [patent_doc_number] => 07274606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Low power chip select (CS) latency option' [patent_app_type] => utility [patent_app_number] => 11/595766 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 25 [patent_no_of_words] => 7665 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274606.pdf [firstpage_image] =>[orig_patent_app_number] => 11595766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/595766
Low power chip select (CS) latency option Nov 8, 2006 Issued
Array ( [id] => 5074194 [patent_doc_number] => 20070014169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Semiconductor memory device and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/522904 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10921 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20070014169.pdf [firstpage_image] =>[orig_patent_app_number] => 11522904 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/522904
Semiconductor memory device and semiconductor integrated circuit Sep 18, 2006 Issued
Array ( [id] => 5607083 [patent_doc_number] => 20060268599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/500342 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6076 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20060268599.pdf [firstpage_image] =>[orig_patent_app_number] => 11500342 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500342
Semiconductor memory device Aug 7, 2006 Issued
Array ( [id] => 882966 [patent_doc_number] => 07355874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Computer memory cards using flash EEprom integrated circuit chips and memory-controller systems' [patent_app_type] => utility [patent_app_number] => 11/461265 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6856 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355874.pdf [firstpage_image] =>[orig_patent_app_number] => 11461265 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461265
Computer memory cards using flash EEprom integrated circuit chips and memory-controller systems Jul 30, 2006 Issued
Array ( [id] => 4686896 [patent_doc_number] => 20080031077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'DAISY CHAINABLE MEMORY CHIP' [patent_app_type] => utility [patent_app_number] => 11/459994 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18486 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20080031077.pdf [firstpage_image] =>[orig_patent_app_number] => 11459994 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459994
Daisy chainable memory chip Jul 25, 2006 Issued
Array ( [id] => 4659314 [patent_doc_number] => 20080028176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'MEMORY SYSTEM HAVING SELF TIMED DAISY CHAINED MEMORY CHIPS' [patent_app_type] => utility [patent_app_number] => 11/459957 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18693 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20080028176.pdf [firstpage_image] =>[orig_patent_app_number] => 11459957 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459957
Memory system having self timed daisy chained memory chips Jul 25, 2006 Issued
Array ( [id] => 4656268 [patent_doc_number] => 20080025129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'DAISY CHAINED MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/459956 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18636 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025129.pdf [firstpage_image] =>[orig_patent_app_number] => 11459956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459956
Daisy chained memory system Jul 25, 2006 Issued
Array ( [id] => 4656269 [patent_doc_number] => 20080025130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'COMPUTER SYSTEM HAVING DAISY CHAINED SELF TIMED MEMORY CHIPS' [patent_app_type] => utility [patent_app_number] => 11/459968 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025130.pdf [firstpage_image] =>[orig_patent_app_number] => 11459968 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459968
Computer system having daisy chained self timed memory chips Jul 25, 2006 Issued
Array ( [id] => 5731493 [patent_doc_number] => 20060256607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Ferroelectric memory devices having a plate line control circuit' [patent_app_type] => utility [patent_app_number] => 11/491872 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7015 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20060256607.pdf [firstpage_image] =>[orig_patent_app_number] => 11491872 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/491872
Ferroelectric memory devices having a plate line control circuit Jul 23, 2006 Issued
Array ( [id] => 5147245 [patent_doc_number] => 20070047299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'METHOD FOR ACCESSING A MULTILEVEL NONVOLATILE MEMORY DEVICE OF THE FLASH NAND TYPE' [patent_app_type] => utility [patent_app_number] => 11/458904 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4192 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047299.pdf [firstpage_image] =>[orig_patent_app_number] => 11458904 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458904
Method for accessing a multilevel nonvolatile memory device of the flash NAND type Jul 19, 2006 Issued
Array ( [id] => 891393 [patent_doc_number] => 07349265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Reading method of a NAND-type memory device and NAND-type memory device' [patent_app_type] => utility [patent_app_number] => 11/458916 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5285 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/349/07349265.pdf [firstpage_image] =>[orig_patent_app_number] => 11458916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458916
Reading method of a NAND-type memory device and NAND-type memory device Jul 19, 2006 Issued
Array ( [id] => 5158673 [patent_doc_number] => 20070171717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Dynamic matching of signal path and reference path for sensing' [patent_app_type] => utility [patent_app_number] => 11/490539 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3918 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20070171717.pdf [firstpage_image] =>[orig_patent_app_number] => 11490539 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490539
Dynamic matching of signal path and reference path for sensing Jul 18, 2006 Issued
Array ( [id] => 5663071 [patent_doc_number] => 20060253667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'PURGE OPERATIONS FOR SOLID-STATE STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 11/458336 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6507 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253667.pdf [firstpage_image] =>[orig_patent_app_number] => 11458336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458336
Purge operations for solid-state storage devices Jul 17, 2006 Issued
Array ( [id] => 4796433 [patent_doc_number] => 20080008019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'High Speed Read-Only Memory' [patent_app_type] => utility [patent_app_number] => 11/309174 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20080008019.pdf [firstpage_image] =>[orig_patent_app_number] => 11309174 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309174
High Speed Read-Only Memory Jul 5, 2006 Abandoned
Array ( [id] => 5251829 [patent_doc_number] => 20070133285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Flash memory device with sector access' [patent_app_type] => utility [patent_app_number] => 11/428816 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3397 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133285.pdf [firstpage_image] =>[orig_patent_app_number] => 11428816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428816
Flash memory device with sector access Jul 4, 2006 Issued
Array ( [id] => 862613 [patent_doc_number] => 07372751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Using redundant memory for extra features' [patent_app_type] => utility [patent_app_number] => 11/473465 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4968 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372751.pdf [firstpage_image] =>[orig_patent_app_number] => 11473465 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/473465
Using redundant memory for extra features Jun 22, 2006 Issued
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