Son Luu Mai

Array ( [id] => 430084 [patent_doc_number] => 07269083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Using redundant memory for extra features' [patent_app_type] => utility [patent_app_number] => 11/473466 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269083.pdf [firstpage_image] =>[orig_patent_app_number] => 11473466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 895091 [patent_doc_number] => 07345919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Semiconductor device that enables simultaneous read and write/read operation' [patent_app_type] => utility [patent_app_number] => 11/453830 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 61 [patent_no_of_words] => 18636 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/345/07345919.pdf [firstpage_image] =>[orig_patent_app_number] => 11453830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 253650 [patent_doc_number] => 07580291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Data register with efficient erase, program verify, and direct bit-line memory access features' [patent_app_type] => utility [patent_app_number] => 11/422960 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/580/07580291.pdf [firstpage_image] =>[orig_patent_app_number] => 11422960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 405540 [patent_doc_number] => 07289375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Data holding circuit' [patent_app_type] => utility [patent_app_number] => 11/444526 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/289/07289375.pdf [firstpage_image] =>[orig_patent_app_number] => 11444526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 416719 [patent_doc_number] => 07280423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-09 [patent_title] => 'Current-mode sensing structure of high-density multiple-port register in embedded flash memory procedure and method for the same' [patent_app_type] => utility [patent_app_number] => 11/443036 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1768 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/280/07280423.pdf [firstpage_image] =>[orig_patent_app_number] => 11443036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4993454 [patent_doc_number] => 20070008799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/443348 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7950 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20070008799.pdf [firstpage_image] =>[orig_patent_app_number] => 11443348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 834764 [patent_doc_number] => 07397686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Memory system combining flash EEPROM and FeRAM' [patent_app_type] => utility [patent_app_number] => 11/443388 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 14129 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397686.pdf [firstpage_image] =>[orig_patent_app_number] => 11443388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5067951 [patent_doc_number] => 20070189052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Memory system' [patent_app_type] => utility [patent_app_number] => 11/443030 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6420 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20070189052.pdf [firstpage_image] =>[orig_patent_app_number] => 11443030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 858834 [patent_doc_number] => 07376033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Semiconductor device and programming method therefor' [patent_app_type] => utility [patent_app_number] => 11/443640 [patent_app_country] => US [patent_app_date] => 2006-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7359 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376033.pdf [firstpage_image] =>[orig_patent_app_number] => 11443640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 919765 [patent_doc_number] => 07324401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Memory device and method having programmable address configurations' [patent_app_type] => utility [patent_app_number] => 11/431164 [patent_app_country] => US [patent_app_date] => 2006-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5837 [patent_no_of_claims] => 88 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/324/07324401.pdf [firstpage_image] =>[orig_patent_app_number] => 11431164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 883150 [patent_doc_number] => 07355922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM' [patent_app_type] => utility [patent_app_number] => 11/429856 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5107 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355922.pdf [firstpage_image] =>[orig_patent_app_number] => 11429856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5015081 [patent_doc_number] => 20070258289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Method of Programming and Erasing a P-Channel BE-SONOS NAND Flash Memory' [patent_app_type] => utility [patent_app_number] => 11/381760 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5523 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20070258289.pdf [firstpage_image] =>[orig_patent_app_number] => 11381760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 422646 [patent_doc_number] => 07274581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-25 [patent_title] => 'Array fault testing approach for TCAMs' [patent_app_type] => utility [patent_app_number] => 11/381540 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5643 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274581.pdf [firstpage_image] =>[orig_patent_app_number] => 11381540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5641544 [patent_doc_number] => 20060279999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Methods of Erasing Flash Memory Devices by Applying Wordline Bias Voltages Having Multiple Levels and Related Flash Memory Devices' [patent_app_type] => utility [patent_app_number] => 11/381556 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4315 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20060279999.pdf [firstpage_image] =>[orig_patent_app_number] => 11381556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 422665 [patent_doc_number] => 07274600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'NAND flash memory with read and verification threshold uniformity' [patent_app_type] => utility [patent_app_number] => 11/415365 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3216 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274600.pdf [firstpage_image] =>[orig_patent_app_number] => 11415365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5782304 [patent_doc_number] => 20060203553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'NAND string wordline delay reduction' [patent_app_type] => utility [patent_app_number] => 11/412217 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4320 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20060203553.pdf [firstpage_image] =>[orig_patent_app_number] => 11412217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 271479 [patent_doc_number] => 07564718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Method for programming a block of memory cells, non-volatile memory device and memory card device' [patent_app_type] => utility [patent_app_number] => 11/402649 [patent_app_country] => US [patent_app_date] => 2006-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8010 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564718.pdf [firstpage_image] =>[orig_patent_app_number] => 11402649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 834879 [patent_doc_number] => 07397726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-08 [patent_title] => 'Flexible RAM clock enable' [patent_app_type] => utility [patent_app_number] => 11/399771 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 12349 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397726.pdf [firstpage_image] =>[orig_patent_app_number] => 11399771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5124707 [patent_doc_number] => 20070236978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Non-volatile Reactive Magnetic Memory device (REMM)' [patent_app_type] => utility [patent_app_number] => 11/398361 [patent_app_country] => US [patent_app_date] => 2006-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3056 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20070236978.pdf [firstpage_image] =>[orig_patent_app_number] => 11398361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5124732 [patent_doc_number] => 20070237003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Flash memory programming and verification with reduced leakage current' [patent_app_type] => utility [patent_app_number] => 11/398415 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6431 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20070237003.pdf [firstpage_image] =>[orig_patent_app_number] => 11398415 [rel_patent_id] =>[rel_patent_doc_number] =>)