Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 578207 [patent_doc_number] => 07466577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Semiconductor storage device having a plurality of stacked memory chips' [patent_app_type] => utility [patent_app_number] => 11/392805 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 11553 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/466/07466577.pdf [firstpage_image] =>[orig_patent_app_number] => 11392805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/392805
Semiconductor storage device having a plurality of stacked memory chips Mar 29, 2006 Issued
Array ( [id] => 5061653 [patent_doc_number] => 20070223292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Method for column redundancy using data latches in solid-state memories' [patent_app_type] => utility [patent_app_number] => 11/389655 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20070223292.pdf [firstpage_image] =>[orig_patent_app_number] => 11389655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/389655
Method for column redundancy using data latches in solid-state memories Mar 23, 2006 Issued
Array ( [id] => 482281 [patent_doc_number] => 07224605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-29 [patent_title] => 'Non-volatile memory with redundancy data buffered in data latches for defective locations' [patent_app_type] => utility [patent_app_number] => 11/388408 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 9883 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224605.pdf [firstpage_image] =>[orig_patent_app_number] => 11388408 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388408
Non-volatile memory with redundancy data buffered in data latches for defective locations Mar 23, 2006 Issued
Array ( [id] => 5061657 [patent_doc_number] => 20070223296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Bitline isolation control to reduce leakage current in memory device' [patent_app_type] => utility [patent_app_number] => 11/387882 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4839 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20070223296.pdf [firstpage_image] =>[orig_patent_app_number] => 11387882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/387882
Bitline isolation control to reduce leakage current in memory device Mar 23, 2006 Abandoned
Array ( [id] => 891300 [patent_doc_number] => 07349233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Memory device with read data from different banks' [patent_app_type] => utility [patent_app_number] => 11/388464 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5839 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/349/07349233.pdf [firstpage_image] =>[orig_patent_app_number] => 11388464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388464
Memory device with read data from different banks Mar 23, 2006 Issued
Array ( [id] => 858777 [patent_doc_number] => 07376010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Nonvolatile semiconductor memory device having protection function for each memory block' [patent_app_type] => utility [patent_app_number] => 11/387818 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 9460 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376010.pdf [firstpage_image] =>[orig_patent_app_number] => 11387818 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/387818
Nonvolatile semiconductor memory device having protection function for each memory block Mar 23, 2006 Issued
Array ( [id] => 387529 [patent_doc_number] => 07304900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/386650 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4770 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304900.pdf [firstpage_image] =>[orig_patent_app_number] => 11386650 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/386650
Semiconductor memory Mar 22, 2006 Issued
Array ( [id] => 437121 [patent_doc_number] => 07262993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/388056 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9395 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262993.pdf [firstpage_image] =>[orig_patent_app_number] => 11388056 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388056
Nonvolatile semiconductor memory device Mar 22, 2006 Issued
Array ( [id] => 5871328 [patent_doc_number] => 20060164876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Multi-transistor memory cells' [patent_app_type] => utility [patent_app_number] => 11/387490 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5511 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20060164876.pdf [firstpage_image] =>[orig_patent_app_number] => 11387490 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/387490
Multi-transistor memory cells Mar 22, 2006 Issued
Array ( [id] => 426303 [patent_doc_number] => 07272063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-18 [patent_title] => 'Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory' [patent_app_type] => utility [patent_app_number] => 11/386048 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6129 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272063.pdf [firstpage_image] =>[orig_patent_app_number] => 11386048 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/386048
Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory Mar 20, 2006 Issued
Array ( [id] => 5061654 [patent_doc_number] => 20070223293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Parallel read for front end compression mode' [patent_app_type] => utility [patent_app_number] => 11/385340 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3254 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20070223293.pdf [firstpage_image] =>[orig_patent_app_number] => 11385340 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385340
Parallel read for front end compression mode Mar 20, 2006 Issued
Array ( [id] => 5751939 [patent_doc_number] => 20060221088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Memory interface control circuit' [patent_app_type] => utility [patent_app_number] => 11/384406 [patent_app_country] => US [patent_app_date] => 2006-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4561 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20060221088.pdf [firstpage_image] =>[orig_patent_app_number] => 11384406 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/384406
Memory interface control circuit Mar 19, 2006 Issued
Array ( [id] => 4987224 [patent_doc_number] => 20070153562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'BIT CELL OF ORGANIC MEMORY' [patent_app_type] => utility [patent_app_number] => 11/308146 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4767 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153562.pdf [firstpage_image] =>[orig_patent_app_number] => 11308146 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308146
Bit cell of organic memory Mar 7, 2006 Issued
Array ( [id] => 5630173 [patent_doc_number] => 20060146641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'High speed DRAM architecture with uniform access latency' [patent_app_type] => utility [patent_app_number] => 11/367589 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7798 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20060146641.pdf [firstpage_image] =>[orig_patent_app_number] => 11367589 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/367589
High speed DRAM architecture with uniform access latency Mar 5, 2006 Issued
Array ( [id] => 5251850 [patent_doc_number] => 20070133306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'ERASING METHOD FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/308018 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3781 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133306.pdf [firstpage_image] =>[orig_patent_app_number] => 11308018 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308018
Erasing method for non-volatile memory Mar 2, 2006 Issued
Array ( [id] => 449172 [patent_doc_number] => 07254082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/363060 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5096 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254082.pdf [firstpage_image] =>[orig_patent_app_number] => 11363060 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/363060
Semiconductor device Feb 27, 2006 Issued
Array ( [id] => 5692848 [patent_doc_number] => 20060152994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Timer lockout circuit for synchronous applications' [patent_app_type] => utility [patent_app_number] => 11/363678 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2748 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20060152994.pdf [firstpage_image] =>[orig_patent_app_number] => 11363678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/363678
Timer lockout circuit for synchronous applications Feb 27, 2006 Issued
Array ( [id] => 5833419 [patent_doc_number] => 20060245249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Nonvolatile memory devices that support virtual page storage using odd-state memory cells and methods of programming same' [patent_app_type] => utility [patent_app_number] => 11/358648 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4842 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245249.pdf [firstpage_image] =>[orig_patent_app_number] => 11358648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358648
Nonvolatile memory devices that support virtual page storage using odd-state memory cells Feb 20, 2006 Issued
Array ( [id] => 842118 [patent_doc_number] => 07391634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Semiconductor memory devices having controllable input/output bit architectures' [patent_app_type] => utility [patent_app_number] => 11/358798 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7471 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391634.pdf [firstpage_image] =>[orig_patent_app_number] => 11358798 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358798
Semiconductor memory devices having controllable input/output bit architectures Feb 20, 2006 Issued
Array ( [id] => 5111720 [patent_doc_number] => 20070195635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Non-volatile memory device with page buffer having dual registers and methods using the same' [patent_app_type] => utility [patent_app_number] => 11/358767 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7007 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195635.pdf [firstpage_image] =>[orig_patent_app_number] => 11358767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358767
Non-volatile memory device with page buffer having dual registers and methods using the same Feb 20, 2006 Issued
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