
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5665887
[patent_doc_number] => 20060171237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/344016
[patent_app_country] => US
[patent_app_date] => 2006-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 17549
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20060171237.pdf
[firstpage_image] =>[orig_patent_app_number] => 11344016
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/344016 | Semiconductor memory device | Jan 31, 2006 | Issued |
Array
(
[id] => 596645
[patent_doc_number] => 07440333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-21
[patent_title] => 'Method of determining voltage compensation for flash memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/340916
[patent_app_country] => US
[patent_app_date] => 2006-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6906
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/440/07440333.pdf
[firstpage_image] =>[orig_patent_app_number] => 11340916
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/340916 | Method of determining voltage compensation for flash memory devices | Jan 26, 2006 | Issued |
Array
(
[id] => 858803
[patent_doc_number] => 07376025
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-20
[patent_title] => 'Method and apparatus for semiconductor device repair with reduced number of programmable elements'
[patent_app_type] => utility
[patent_app_number] => 11/340886
[patent_app_country] => US
[patent_app_date] => 2006-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6607
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/376/07376025.pdf
[firstpage_image] =>[orig_patent_app_number] => 11340886
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/340886 | Method and apparatus for semiconductor device repair with reduced number of programmable elements | Jan 26, 2006 | Issued |
Array
(
[id] => 5879278
[patent_doc_number] => 20060168505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Integrated memory device and method for operating the same'
[patent_app_type] => utility
[patent_app_number] => 11/339846
[patent_app_country] => US
[patent_app_date] => 2006-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14968
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20060168505.pdf
[firstpage_image] =>[orig_patent_app_number] => 11339846
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/339846 | Integrated memory device and method for operating the same | Jan 25, 2006 | Issued |
Array
(
[id] => 5840570
[patent_doc_number] => 20060120186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Semiconductor memory device with shift redundancy circuits'
[patent_app_type] => utility
[patent_app_number] => 11/337493
[patent_app_country] => US
[patent_app_date] => 2006-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8398
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20060120186.pdf
[firstpage_image] =>[orig_patent_app_number] => 11337493
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/337493 | Semiconductor memory device with shift redundancy circuits | Jan 23, 2006 | Issued |
Array
(
[id] => 5660278
[patent_doc_number] => 20060250874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'Refresh control circuit and method thereof and bank address signal change circuit and methods thereof'
[patent_app_type] => utility
[patent_app_number] => 11/332477
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3770
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20060250874.pdf
[firstpage_image] =>[orig_patent_app_number] => 11332477
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/332477 | Refresh control circuit and method thereof and bank address signal change circuit and methods thereof | Jan 16, 2006 | Issued |
Array
(
[id] => 5187171
[patent_doc_number] => 20070165479
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Local wordline driver scheme to avoid fails due to floating wordline in a segmented wordline driver scheme'
[patent_app_type] => utility
[patent_app_number] => 11/333043
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4687
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0165/20070165479.pdf
[firstpage_image] =>[orig_patent_app_number] => 11333043
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/333043 | Local wordline driver scheme to avoid fails due to floating wordline in a segmented wordline driver scheme | Jan 16, 2006 | Abandoned |
Array
(
[id] => 5647446
[patent_doc_number] => 20060133178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'System and method for destructive purge of memory device'
[patent_app_type] => utility
[patent_app_number] => 11/332197
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3273
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20060133178.pdf
[firstpage_image] =>[orig_patent_app_number] => 11332197
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/332197 | System and method for destructive purge of memory device | Jan 16, 2006 | Issued |
Array
(
[id] => 5187161
[patent_doc_number] => 20070165469
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Test parallelism increase by tester controllable switching of chip select groups'
[patent_app_type] => utility
[patent_app_number] => 11/333037
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3338
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0165/20070165469.pdf
[firstpage_image] =>[orig_patent_app_number] => 11333037
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/333037 | Test parallelism increase by tester controllable switching of chip select groups | Jan 16, 2006 | Issued |
Array
(
[id] => 5187150
[patent_doc_number] => 20070165458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Random cache read using a double memory'
[patent_app_type] => utility
[patent_app_number] => 11/332241
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3237
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0165/20070165458.pdf
[firstpage_image] =>[orig_patent_app_number] => 11332241
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/332241 | Random cache read using a double memory | Jan 16, 2006 | Issued |
Array
(
[id] => 346119
[patent_doc_number] => 07499310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-03
[patent_title] => 'Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/332605
[patent_app_country] => US
[patent_app_date] => 2006-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5971
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/499/07499310.pdf
[firstpage_image] =>[orig_patent_app_number] => 11332605
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/332605 | Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor | Jan 12, 2006 | Issued |
Array
(
[id] => 808441
[patent_doc_number] => 07420848
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-02
[patent_title] => 'Method, system, and circuit for operating a non-volatile memory array'
[patent_app_type] => utility
[patent_app_number] => 11/328015
[patent_app_country] => US
[patent_app_date] => 2006-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4195
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/420/07420848.pdf
[firstpage_image] =>[orig_patent_app_number] => 11328015
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/328015 | Method, system, and circuit for operating a non-volatile memory array | Jan 8, 2006 | Issued |
Array
(
[id] => 525853
[patent_doc_number] => 07193882
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-20
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/319365
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 23
[patent_no_of_words] => 6372
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/193/07193882.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319365
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319365 | Semiconductor memory device | Dec 28, 2005 | Issued |
Array
(
[id] => 5140398
[patent_doc_number] => 20070002614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'METHOD OF CONTROLLING PROGRAM OPERATION OF FLASH MEMORY DEVICE WITH REDUCED PROGRAM TIME'
[patent_app_type] => utility
[patent_app_number] => 11/306472
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5210
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20070002614.pdf
[firstpage_image] =>[orig_patent_app_number] => 11306472
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/306472 | Method of controlling program operation of flash memory device with reduced program time | Dec 28, 2005 | Issued |
Array
(
[id] => 842178
[patent_doc_number] => 07391669
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-24
[patent_title] => 'Semiconductor memory device and core layout thereof'
[patent_app_type] => utility
[patent_app_number] => 11/316878
[patent_app_country] => US
[patent_app_date] => 2005-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5007
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/391/07391669.pdf
[firstpage_image] =>[orig_patent_app_number] => 11316878
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/316878 | Semiconductor memory device and core layout thereof | Dec 26, 2005 | Issued |
Array
(
[id] => 7600854
[patent_doc_number] => 07385855
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-10
[patent_title] => 'Nonvolatile memory device having self reprogramming function'
[patent_app_type] => utility
[patent_app_number] => 11/306370
[patent_app_country] => US
[patent_app_date] => 2005-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3137
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/385/07385855.pdf
[firstpage_image] =>[orig_patent_app_number] => 11306370
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/306370 | Nonvolatile memory device having self reprogramming function | Dec 25, 2005 | Issued |
Array
(
[id] => 413297
[patent_doc_number] => 07283387
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-16
[patent_title] => 'Phase change random access memory device having variable drive voltage circuit'
[patent_app_type] => utility
[patent_app_number] => 11/316256
[patent_app_country] => US
[patent_app_date] => 2005-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 6939
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/283/07283387.pdf
[firstpage_image] =>[orig_patent_app_number] => 11316256
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/316256 | Phase change random access memory device having variable drive voltage circuit | Dec 22, 2005 | Issued |
Array
(
[id] => 478599
[patent_doc_number] => 07227776
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Phase change random access memory (PRAM) device'
[patent_app_type] => utility
[patent_app_number] => 11/315130
[patent_app_country] => US
[patent_app_date] => 2005-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3951
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/227/07227776.pdf
[firstpage_image] =>[orig_patent_app_number] => 11315130
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/315130 | Phase change random access memory (PRAM) device | Dec 22, 2005 | Issued |
Array
(
[id] => 471340
[patent_doc_number] => 07233535
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-19
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/315698
[patent_app_country] => US
[patent_app_date] => 2005-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 6060
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/233/07233535.pdf
[firstpage_image] =>[orig_patent_app_number] => 11315698
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/315698 | Semiconductor memory device | Dec 21, 2005 | Issued |
Array
(
[id] => 921071
[patent_doc_number] => 07321511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-22
[patent_title] => 'Semiconductor device and method for controlling operation thereof'
[patent_app_type] => utility
[patent_app_number] => 11/316800
[patent_app_country] => US
[patent_app_date] => 2005-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 5750
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/321/07321511.pdf
[firstpage_image] =>[orig_patent_app_number] => 11316800
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/316800 | Semiconductor device and method for controlling operation thereof | Dec 21, 2005 | Issued |