Son Luu Mai

Array ( [id] => 4987224 [patent_doc_number] => 20070153562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'BIT CELL OF ORGANIC MEMORY' [patent_app_type] => utility [patent_app_number] => 11/308146 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4767 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153562.pdf [firstpage_image] =>[orig_patent_app_number] => 11308146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5630173 [patent_doc_number] => 20060146641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'High speed DRAM architecture with uniform access latency' [patent_app_type] => utility [patent_app_number] => 11/367589 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7798 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20060146641.pdf [firstpage_image] =>[orig_patent_app_number] => 11367589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5251850 [patent_doc_number] => 20070133306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'ERASING METHOD FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/308018 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3781 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133306.pdf [firstpage_image] =>[orig_patent_app_number] => 11308018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 449172 [patent_doc_number] => 07254082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/363060 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5096 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254082.pdf [firstpage_image] =>[orig_patent_app_number] => 11363060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5692848 [patent_doc_number] => 20060152994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Timer lockout circuit for synchronous applications' [patent_app_type] => utility [patent_app_number] => 11/363678 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2748 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20060152994.pdf [firstpage_image] =>[orig_patent_app_number] => 11363678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5111720 [patent_doc_number] => 20070195635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Non-volatile memory device with page buffer having dual registers and methods using the same' [patent_app_type] => utility [patent_app_number] => 11/358767 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7007 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195635.pdf [firstpage_image] =>[orig_patent_app_number] => 11358767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5833419 [patent_doc_number] => 20060245249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Nonvolatile memory devices that support virtual page storage using odd-state memory cells and methods of programming same' [patent_app_type] => utility [patent_app_number] => 11/358648 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4842 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245249.pdf [firstpage_image] =>[orig_patent_app_number] => 11358648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 842118 [patent_doc_number] => 07391634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Semiconductor memory devices having controllable input/output bit architectures' [patent_app_type] => utility [patent_app_number] => 11/358798 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7471 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391634.pdf [firstpage_image] =>[orig_patent_app_number] => 11358798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5665887 [patent_doc_number] => 20060171237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/344016 [patent_app_country] => US [patent_app_date] => 2006-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20060171237.pdf [firstpage_image] =>[orig_patent_app_number] => 11344016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 858803 [patent_doc_number] => 07376025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Method and apparatus for semiconductor device repair with reduced number of programmable elements' [patent_app_type] => utility [patent_app_number] => 11/340886 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6607 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376025.pdf [firstpage_image] =>[orig_patent_app_number] => 11340886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 596645 [patent_doc_number] => 07440333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Method of determining voltage compensation for flash memory devices' [patent_app_type] => utility [patent_app_number] => 11/340916 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6906 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/440/07440333.pdf [firstpage_image] =>[orig_patent_app_number] => 11340916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5879278 [patent_doc_number] => 20060168505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Integrated memory device and method for operating the same' [patent_app_type] => utility [patent_app_number] => 11/339846 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14968 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20060168505.pdf [firstpage_image] =>[orig_patent_app_number] => 11339846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5840570 [patent_doc_number] => 20060120186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Semiconductor memory device with shift redundancy circuits' [patent_app_type] => utility [patent_app_number] => 11/337493 [patent_app_country] => US [patent_app_date] => 2006-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8398 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20060120186.pdf [firstpage_image] =>[orig_patent_app_number] => 11337493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5660278 [patent_doc_number] => 20060250874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Refresh control circuit and method thereof and bank address signal change circuit and methods thereof' [patent_app_type] => utility [patent_app_number] => 11/332477 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3770 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250874.pdf [firstpage_image] =>[orig_patent_app_number] => 11332477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5647446 [patent_doc_number] => 20060133178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'System and method for destructive purge of memory device' [patent_app_type] => utility [patent_app_number] => 11/332197 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133178.pdf [firstpage_image] =>[orig_patent_app_number] => 11332197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5187161 [patent_doc_number] => 20070165469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Test parallelism increase by tester controllable switching of chip select groups' [patent_app_type] => utility [patent_app_number] => 11/333037 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165469.pdf [firstpage_image] =>[orig_patent_app_number] => 11333037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5187171 [patent_doc_number] => 20070165479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Local wordline driver scheme to avoid fails due to floating wordline in a segmented wordline driver scheme' [patent_app_type] => utility [patent_app_number] => 11/333043 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4687 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165479.pdf [firstpage_image] =>[orig_patent_app_number] => 11333043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5187150 [patent_doc_number] => 20070165458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Random cache read using a double memory' [patent_app_type] => utility [patent_app_number] => 11/332241 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165458.pdf [firstpage_image] =>[orig_patent_app_number] => 11332241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 346119 [patent_doc_number] => 07499310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor' [patent_app_type] => utility [patent_app_number] => 11/332605 [patent_app_country] => US [patent_app_date] => 2006-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5971 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499310.pdf [firstpage_image] =>[orig_patent_app_number] => 11332605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 808441 [patent_doc_number] => 07420848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Method, system, and circuit for operating a non-volatile memory array' [patent_app_type] => utility [patent_app_number] => 11/328015 [patent_app_country] => US [patent_app_date] => 2006-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4195 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/420/07420848.pdf [firstpage_image] =>[orig_patent_app_number] => 11328015 [rel_patent_id] =>[rel_patent_doc_number] =>)