Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 526127 [patent_doc_number] => 07193905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-20 [patent_title] => 'RRAM flipflop rcell memory generator' [patent_app_type] => utility [patent_app_number] => 11/259228 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1809 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193905.pdf [firstpage_image] =>[orig_patent_app_number] => 11259228 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/259228
RRAM flipflop rcell memory generator Oct 24, 2005 Issued
Array ( [id] => 4668462 [patent_doc_number] => 20080043522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Nonvolatile Semiconductor Memory Device and Phase Change Memory Device' [patent_app_type] => utility [patent_app_number] => 11/666160 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7510 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20080043522.pdf [firstpage_image] =>[orig_patent_app_number] => 11666160 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/666160
Nonvolatile semiconductor memory device and phase change memory device Oct 24, 2005 Issued
Array ( [id] => 5840945 [patent_doc_number] => 20060120359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/258565 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9450 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20060120359.pdf [firstpage_image] =>[orig_patent_app_number] => 11258565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258565
Semiconductor memory device having a reduced number of pins Oct 24, 2005 Issued
Array ( [id] => 5039386 [patent_doc_number] => 20070091668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Magnetic memory device and methods for making a magnetic memory device' [patent_app_type] => utility [patent_app_number] => 11/255606 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4373 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20070091668.pdf [firstpage_image] =>[orig_patent_app_number] => 11255606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/255606
Magnetic memory device and methods for making a magnetic memory device Oct 20, 2005 Issued
Array ( [id] => 525797 [patent_doc_number] => 07193877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-20 [patent_title] => 'Content addressable memory with reduced test time' [patent_app_type] => utility [patent_app_number] => 11/256066 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8958 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193877.pdf [firstpage_image] =>[orig_patent_app_number] => 11256066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256066
Content addressable memory with reduced test time Oct 20, 2005 Issued
Array ( [id] => 455630 [patent_doc_number] => 07248528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Refresh control method of a semiconductor memory device and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/254722 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 45 [patent_no_of_words] => 19482 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248528.pdf [firstpage_image] =>[orig_patent_app_number] => 11254722 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254722
Refresh control method of a semiconductor memory device and semiconductor memory device Oct 20, 2005 Issued
Array ( [id] => 517826 [patent_doc_number] => 07196942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Configuration memory structure' [patent_app_type] => utility [patent_app_number] => 11/254558 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196942.pdf [firstpage_image] =>[orig_patent_app_number] => 11254558 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254558
Configuration memory structure Oct 19, 2005 Issued
Array ( [id] => 542723 [patent_doc_number] => 07180773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Magnetic memory device' [patent_app_type] => utility [patent_app_number] => 11/253696 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6410 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180773.pdf [firstpage_image] =>[orig_patent_app_number] => 11253696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/253696
Magnetic memory device Oct 19, 2005 Issued
Array ( [id] => 610326 [patent_doc_number] => 07151712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-19 [patent_title] => 'Row decoder with low gate induce drain leakage current' [patent_app_type] => utility [patent_app_number] => 11/163436 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2690 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151712.pdf [firstpage_image] =>[orig_patent_app_number] => 11163436 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163436
Row decoder with low gate induce drain leakage current Oct 18, 2005 Issued
Array ( [id] => 4981705 [patent_doc_number] => 20070086263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Clock reset address decoder for block memory' [patent_app_type] => utility [patent_app_number] => 11/252094 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3919 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20070086263.pdf [firstpage_image] =>[orig_patent_app_number] => 11252094 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252094
Clock reset address decoder for block memory Oct 16, 2005 Issued
Array ( [id] => 543094 [patent_doc_number] => 07180804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-20 [patent_title] => 'High performance sense amplifier and method thereof for memory system' [patent_app_type] => utility [patent_app_number] => 11/253052 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180804.pdf [firstpage_image] =>[orig_patent_app_number] => 11253052 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/253052
High performance sense amplifier and method thereof for memory system Oct 16, 2005 Issued
Array ( [id] => 518016 [patent_doc_number] => 07196963 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'Address isolation for user-defined configuration memory in programmable devices' [patent_app_type] => utility [patent_app_number] => 11/251682 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4238 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196963.pdf [firstpage_image] =>[orig_patent_app_number] => 11251682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251682
Address isolation for user-defined configuration memory in programmable devices Oct 16, 2005 Issued
Array ( [id] => 621701 [patent_doc_number] => 07142466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Determining optimal time instances to sense the output of a memory array which can generate data outputs with variable delay' [patent_app_type] => utility [patent_app_number] => 11/163318 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5261 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/142/07142466.pdf [firstpage_image] =>[orig_patent_app_number] => 11163318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163318
Determining optimal time instances to sense the output of a memory array which can generate data outputs with variable delay Oct 13, 2005 Issued
Array ( [id] => 5879797 [patent_doc_number] => 20060028879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/247167 [patent_app_country] => US [patent_app_date] => 2005-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8480 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20060028879.pdf [firstpage_image] =>[orig_patent_app_number] => 11247167 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/247167
Semiconductor device Oct 11, 2005 Issued
Array ( [id] => 5589727 [patent_doc_number] => 20060039178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Device having a memory array storing each bit in multiple memory cells' [patent_app_type] => utility [patent_app_number] => 11/245725 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8258 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20060039178.pdf [firstpage_image] =>[orig_patent_app_number] => 11245725 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/245725
Device and method having a memory array storing each bit in multiple memory cells Oct 5, 2005 Issued
Array ( [id] => 5192903 [patent_doc_number] => 20070081385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => '[METHOD FOR MANAGING MEMORY BLOCKS IN FLASH MEMORY]' [patent_app_type] => utility [patent_app_number] => 11/163128 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1544 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20070081385.pdf [firstpage_image] =>[orig_patent_app_number] => 11163128 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163128
Method for managing memory blocks in flash memory Oct 5, 2005 Issued
Array ( [id] => 486974 [patent_doc_number] => 07221604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Memory structure with repairing function and repairing method thereof' [patent_app_type] => utility [patent_app_number] => 11/163126 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5968 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221604.pdf [firstpage_image] =>[orig_patent_app_number] => 11163126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163126
Memory structure with repairing function and repairing method thereof Oct 4, 2005 Issued
Array ( [id] => 463485 [patent_doc_number] => 07242620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Nonvolatile semiconductor memory device and an operation method thereof' [patent_app_type] => utility [patent_app_number] => 11/240510 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242620.pdf [firstpage_image] =>[orig_patent_app_number] => 11240510 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/240510
Nonvolatile semiconductor memory device and an operation method thereof Oct 2, 2005 Issued
Array ( [id] => 628420 [patent_doc_number] => 07136323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Apparatus and method for generating a variable-frequency clock' [patent_app_type] => utility [patent_app_number] => 11/162972 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/136/07136323.pdf [firstpage_image] =>[orig_patent_app_number] => 11162972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162972
Apparatus and method for generating a variable-frequency clock Sep 28, 2005 Issued
Array ( [id] => 471325 [patent_doc_number] => 07233527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-19 [patent_title] => 'Nonvolatile memory structure' [patent_app_type] => utility [patent_app_number] => 11/162730 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3874 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/233/07233527.pdf [firstpage_image] =>[orig_patent_app_number] => 11162730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162730
Nonvolatile memory structure Sep 20, 2005 Issued
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