
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5763185
[patent_doc_number] => 20060017124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Bistable magnetic device using soft magnetic intermediary material'
[patent_app_type] => utility
[patent_app_number] => 11/223548
[patent_app_country] => US
[patent_app_date] => 2005-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9300
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20060017124.pdf
[firstpage_image] =>[orig_patent_app_number] => 11223548
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/223548 | Bistable magnetic device using soft magnetic intermediary material | Sep 8, 2005 | Issued |
Array
(
[id] => 5765118
[patent_doc_number] => 20060018180
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Nonvolatile semiconductor memory with x8/x16 operation mode using address control'
[patent_app_type] => utility
[patent_app_number] => 11/209483
[patent_app_country] => US
[patent_app_date] => 2005-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4688
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20060018180.pdf
[firstpage_image] =>[orig_patent_app_number] => 11209483
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/209483 | Nonvolatile semiconductor memory with x8/x16 operation mode using address control | Aug 21, 2005 | Abandoned |
Array
(
[id] => 478641
[patent_doc_number] => 07227792
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same'
[patent_app_type] => utility
[patent_app_number] => 11/202880
[patent_app_country] => US
[patent_app_date] => 2005-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 21903
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/227/07227792.pdf
[firstpage_image] =>[orig_patent_app_number] => 11202880
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/202880 | Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same | Aug 11, 2005 | Issued |
Array
(
[id] => 628410
[patent_doc_number] => 07136317
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-11-14
[patent_title] => 'DRAM with self-resetting data path for reduced power consumption'
[patent_app_type] => utility
[patent_app_number] => 11/161628
[patent_app_country] => US
[patent_app_date] => 2005-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3873
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/136/07136317.pdf
[firstpage_image] =>[orig_patent_app_number] => 11161628
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/161628 | DRAM with self-resetting data path for reduced power consumption | Aug 9, 2005 | Issued |
Array
(
[id] => 7220419
[patent_doc_number] => 20050254290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-17
[patent_title] => 'Thin film magnetic memory device including memory cells having a magnetic tunnel junction'
[patent_app_type] => utility
[patent_app_number] => 11/187910
[patent_app_country] => US
[patent_app_date] => 2005-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 47
[patent_no_of_words] => 23536
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0254/20050254290.pdf
[firstpage_image] =>[orig_patent_app_number] => 11187910
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/187910 | Thin film magnetic memory device including memory cells having a magnetic tunnel junction | Jul 24, 2005 | Issued |
Array
(
[id] => 5240980
[patent_doc_number] => 20070019471
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Reduction of programming time in electrically programmable devices'
[patent_app_type] => utility
[patent_app_number] => 11/188612
[patent_app_country] => US
[patent_app_date] => 2005-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2923
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20070019471.pdf
[firstpage_image] =>[orig_patent_app_number] => 11188612
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/188612 | Reduction of programming time in electrically programmable devices | Jul 24, 2005 | Issued |
Array
(
[id] => 874823
[patent_doc_number] => 07362619
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-22
[patent_title] => 'Data strobe synchronization circuit and method for double data rate, multi-bit writes'
[patent_app_type] => utility
[patent_app_number] => 11/187058
[patent_app_country] => US
[patent_app_date] => 2005-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4506
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/362/07362619.pdf
[firstpage_image] =>[orig_patent_app_number] => 11187058
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/187058 | Data strobe synchronization circuit and method for double data rate, multi-bit writes | Jul 21, 2005 | Issued |
Array
(
[id] => 5792377
[patent_doc_number] => 20060013058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Phase change memory device for use in a burst read operation and a data reading method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/184184
[patent_app_country] => US
[patent_app_date] => 2005-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4030
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20060013058.pdf
[firstpage_image] =>[orig_patent_app_number] => 11184184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/184184 | Phase change memory device for use in a burst read operation and a data reading method thereof | Jul 18, 2005 | Issued |
Array
(
[id] => 5074165
[patent_doc_number] => 20070014140
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-18
[patent_title] => 'Nonvolatile semiconductor memory apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/182374
[patent_app_country] => US
[patent_app_date] => 2005-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4143
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20070014140.pdf
[firstpage_image] =>[orig_patent_app_number] => 11182374
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/182374 | Nonvolatile semiconductor memory apparatus | Jul 14, 2005 | Issued |
Array
(
[id] => 5797901
[patent_doc_number] => 20060034137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'Programmable memory device with an improved redundancy structure'
[patent_app_type] => utility
[patent_app_number] => 11/181364
[patent_app_country] => US
[patent_app_date] => 2005-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7152
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20060034137.pdf
[firstpage_image] =>[orig_patent_app_number] => 11181364
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/181364 | Programmable memory device with an improved redundancy structure | Jul 13, 2005 | Issued |
Array
(
[id] => 433667
[patent_doc_number] => 07266039
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-04
[patent_title] => 'Circuitry and method for adjusting signal length'
[patent_app_type] => utility
[patent_app_number] => 11/178169
[patent_app_country] => US
[patent_app_date] => 2005-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2848
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/266/07266039.pdf
[firstpage_image] =>[orig_patent_app_number] => 11178169
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/178169 | Circuitry and method for adjusting signal length | Jul 7, 2005 | Issued |
Array
(
[id] => 538217
[patent_doc_number] => 07184349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/172894
[patent_app_country] => US
[patent_app_date] => 2005-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 9793
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/184/07184349.pdf
[firstpage_image] =>[orig_patent_app_number] => 11172894
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/172894 | Semiconductor memory device | Jul 4, 2005 | Issued |
Array
(
[id] => 5140394
[patent_doc_number] => 20070002610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Reverse-bias method for writing memory cells in a memory array'
[patent_app_type] => utility
[patent_app_number] => 11/174234
[patent_app_country] => US
[patent_app_date] => 2005-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4148
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20070002610.pdf
[firstpage_image] =>[orig_patent_app_number] => 11174234
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/174234 | Reverse-bias method for writing memory cells in a memory array | Jun 30, 2005 | Issued |
Array
(
[id] => 617862
[patent_doc_number] => 07145809
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-12-05
[patent_title] => 'Method for programming multi-level cell'
[patent_app_type] => utility
[patent_app_number] => 11/172694
[patent_app_country] => US
[patent_app_date] => 2005-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 4819
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/145/07145809.pdf
[firstpage_image] =>[orig_patent_app_number] => 11172694
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/172694 | Method for programming multi-level cell | Jun 30, 2005 | Issued |
Array
(
[id] => 5636126
[patent_doc_number] => 20060067099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'One-time programmable (OTP) memory devices enabling programming based on protected status and methods of operating same'
[patent_app_type] => utility
[patent_app_number] => 11/173634
[patent_app_country] => US
[patent_app_date] => 2005-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4640
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20060067099.pdf
[firstpage_image] =>[orig_patent_app_number] => 11173634
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/173634 | One-time programmable (OTP) memory devices enabling programming based on protected status and methods of operating same | Jun 30, 2005 | Issued |
Array
(
[id] => 455560
[patent_doc_number] => 07248510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-24
[patent_title] => 'Circuits that generate an internal supply voltage and semiconductor memory devices that include those circuits'
[patent_app_type] => utility
[patent_app_number] => 11/172256
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4860
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/248/07248510.pdf
[firstpage_image] =>[orig_patent_app_number] => 11172256
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/172256 | Circuits that generate an internal supply voltage and semiconductor memory devices that include those circuits | Jun 29, 2005 | Issued |
Array
(
[id] => 512108
[patent_doc_number] => 07203096
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-10
[patent_title] => 'Method and apparatus for sensing a state of a memory cell'
[patent_app_type] => utility
[patent_app_number] => 11/172367
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6706
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/203/07203096.pdf
[firstpage_image] =>[orig_patent_app_number] => 11172367
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/172367 | Method and apparatus for sensing a state of a memory cell | Jun 29, 2005 | Issued |
Array
(
[id] => 459586
[patent_doc_number] => 07245521
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-17
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 11/169800
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 6027
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/245/07245521.pdf
[firstpage_image] =>[orig_patent_app_number] => 11169800
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/169800 | Semiconductor integrated circuit device | Jun 29, 2005 | Issued |
Array
(
[id] => 5140404
[patent_doc_number] => 20070002620
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'MEMORY DEVICE AND METHOD FOR ERASING MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/170950
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1877
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20070002620.pdf
[firstpage_image] =>[orig_patent_app_number] => 11170950
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/170950 | Memory device and method for erasing memory | Jun 29, 2005 | Issued |
Array
(
[id] => 5140430
[patent_doc_number] => 20070002646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Apparatus and method for repairing a semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 11/170260
[patent_app_country] => US
[patent_app_date] => 2005-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5009
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20070002646.pdf
[firstpage_image] =>[orig_patent_app_number] => 11170260
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/170260 | Apparatus and method for repairing a semiconductor memory | Jun 28, 2005 | Issued |