Search

Son Luu Mai

Examiner (ID: 3402, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18068139 [patent_doc_number] => 20220399227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => Semiconductor Device Structures [patent_app_type] => utility [patent_app_number] => 17/815177 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815177
Semiconductor device structures Jul 25, 2022 Issued
Array ( [id] => 19428293 [patent_doc_number] => 12087727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Joint structure in semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/872023 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 20552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872023 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872023
Joint structure in semiconductor package and manufacturing method thereof Jul 24, 2022 Issued
Array ( [id] => 20360174 [patent_doc_number] => 12476179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Semiconductor package including through-silicon via and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/871449 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 31 [patent_no_of_words] => 2061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871449
Semiconductor package including through-silicon via and method of forming the same Jul 21, 2022 Issued
Array ( [id] => 17984004 [patent_doc_number] => 20220350041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SILICON PHOTOMULTIPLIERS WITH SPLIT MICROCELLS [patent_app_type] => utility [patent_app_number] => 17/813872 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813872
Silicon photomultipliers with split microcells Jul 19, 2022 Issued
Array ( [id] => 17993317 [patent_doc_number] => 20220359354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Bump Joint Structure with Distortion and Method Forming Same [patent_app_type] => utility [patent_app_number] => 17/813820 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813820
Bump joint structure with distortion and method forming same Jul 19, 2022 Issued
Array ( [id] => 20191249 [patent_doc_number] => 12402389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Semiconductor arrangement with airgap and method of forming [patent_app_type] => utility [patent_app_number] => 17/869571 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869571
Semiconductor arrangement with airgap and method of forming Jul 19, 2022 Issued
Array ( [id] => 18162246 [patent_doc_number] => 20230028839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => DETECTION DEVICE [patent_app_type] => utility [patent_app_number] => 17/859251 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17859251 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/859251
Detection device Jul 6, 2022 Issued
Array ( [id] => 18882972 [patent_doc_number] => 20240006341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SEMICONDUCTOR PACKAGE WITH EXTENDED STIFFENER [patent_app_type] => utility [patent_app_number] => 17/857059 [patent_app_country] => US [patent_app_date] => 2022-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857059
SEMICONDUCTOR PACKAGE WITH EXTENDED STIFFENER Jul 3, 2022 Pending
Array ( [id] => 19524057 [patent_doc_number] => 12125797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Package structure with fan-out feature [patent_app_type] => utility [patent_app_number] => 17/856154 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856154
Package structure with fan-out feature Jun 30, 2022 Issued
Array ( [id] => 18882927 [patent_doc_number] => 20240006296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => BUILD UP MATERIAL ARCHITECTURE FOR MICROELECTRONIC PACKAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/856780 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856780
BUILD UP MATERIAL ARCHITECTURE FOR MICROELECTRONIC PACKAGE DEVICE Jun 30, 2022 Pending
Array ( [id] => 18883012 [patent_doc_number] => 20240006381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THROUGH DIELECTRIC VIA [patent_app_type] => utility [patent_app_number] => 17/854728 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854728
MICROELECTRONIC ASSEMBLIES INCLUDING STACKED DIES COUPLED BY A THROUGH DIELECTRIC VIA Jun 29, 2022 Pending
Array ( [id] => 18868207 [patent_doc_number] => 20230422644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => VERTICAL PHASE CHANGE SWITCH DEVICES AND METHODS [patent_app_type] => utility [patent_app_number] => 17/851036 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851036
Vertical phase change switch utilizing a thermally conductive sidewall dielectric for high-efficiency heating Jun 27, 2022 Issued
Array ( [id] => 19812416 [patent_doc_number] => 12243829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Semiconductor package including cavity-mounted device [patent_app_type] => utility [patent_app_number] => 17/808889 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 7725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17808889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/808889
Semiconductor package including cavity-mounted device Jun 23, 2022 Issued
Array ( [id] => 18177356 [patent_doc_number] => 20230038085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => METHOD OF MANUFACTURING INORGANIC OXIDE PARTICLE, METHOD OF MANUFACTURING INORGANIC OXIDE LAYER, AND LIGHT-EMITTING DEVICE INCLUDING INORGANIC OXIDE LAYER MANUFACTURED BY THE METHOD [patent_app_type] => utility [patent_app_number] => 17/849542 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849542
Method of manufacturing inorganic oxide particle, method of manufacturing inorganic oxide layer, and light-emitting device including inorganic oxide layer manufactured by the method Jun 23, 2022 Issued
Array ( [id] => 18865974 [patent_doc_number] => 20230420411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES [patent_app_type] => utility [patent_app_number] => 17/846153 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846153
PACKAGE ARCHITECTURE OF THREE-DIMENSIONAL INTERCONNECT CUBE WITH INTEGRATED CIRCUIT DIES HAVING PLANARIZED EDGES Jun 21, 2022 Pending
Array ( [id] => 18500532 [patent_doc_number] => 20230223326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => CHIP PACKAGE STRUCTURE AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/844200 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844200
Chip package structure and storage system Jun 19, 2022 Issued
Array ( [id] => 19341504 [patent_doc_number] => 12051701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Distributed FET back-bias network [patent_app_type] => utility [patent_app_number] => 17/844590 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8169 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844590
Distributed FET back-bias network Jun 19, 2022 Issued
Array ( [id] => 18983613 [patent_doc_number] => 11908802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Multi-chip package with high density interconnects [patent_app_type] => utility [patent_app_number] => 17/842600 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7308 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842600
Multi-chip package with high density interconnects Jun 15, 2022 Issued
Array ( [id] => 20205582 [patent_doc_number] => 12408378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor structure and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 17/842103 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4539 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842103
Semiconductor structure and method for manufacturing same Jun 15, 2022 Issued
Array ( [id] => 17900881 [patent_doc_number] => 20220310543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR PACKAGES HAVING CONDUCTIVE PILLARS WITH INCLINED SURFACES [patent_app_type] => utility [patent_app_number] => 17/841683 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841683
Semiconductor packages having conductive pillars with inclined surfaces Jun 15, 2022 Issued
Menu