
Son Luu Mai
Examiner (ID: 18155)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818 |
| Total Applications | 3063 |
| Issued Applications | 2917 |
| Pending Applications | 45 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 430011
[patent_doc_number] => 07269057
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Method for connecting circuit elements within an integrated circuit for reducing single-event upsets'
[patent_app_type] => utility
[patent_app_number] => 11/116024
[patent_app_country] => US
[patent_app_date] => 2005-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2012
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/269/07269057.pdf
[firstpage_image] =>[orig_patent_app_number] => 11116024
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/116024 | Method for connecting circuit elements within an integrated circuit for reducing single-event upsets | Apr 26, 2005 | Issued |
Array
(
[id] => 684196
[patent_doc_number] => 07082059
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-25
[patent_title] => 'Position based erase verification levels in a flash memory device'
[patent_app_type] => utility
[patent_app_number] => 11/113833
[patent_app_country] => US
[patent_app_date] => 2005-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2291
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/082/07082059.pdf
[firstpage_image] =>[orig_patent_app_number] => 11113833
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/113833 | Position based erase verification levels in a flash memory device | Apr 24, 2005 | Issued |
Array
(
[id] => 775980
[patent_doc_number] => 07002825
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Word line arrangement having segmented word lines'
[patent_app_type] => utility
[patent_app_number] => 11/103184
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 11411
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/002/07002825.pdf
[firstpage_image] =>[orig_patent_app_number] => 11103184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103184 | Word line arrangement having segmented word lines | Apr 10, 2005 | Issued |
Array
(
[id] => 547138
[patent_doc_number] => 07177169
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Word line arrangement having multi-layer word line segments for three-dimensional memory array'
[patent_app_type] => utility
[patent_app_number] => 11/103185
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 11351
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/177/07177169.pdf
[firstpage_image] =>[orig_patent_app_number] => 11103185
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103185 | Word line arrangement having multi-layer word line segments for three-dimensional memory array | Apr 10, 2005 | Issued |
Array
(
[id] => 661170
[patent_doc_number] => 07106652
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Word line arrangement having multi-layer word line segments for three-dimensional memory array'
[patent_app_type] => utility
[patent_app_number] => 11/103249
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 11410
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/106/07106652.pdf
[firstpage_image] =>[orig_patent_app_number] => 11103249
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103249 | Word line arrangement having multi-layer word line segments for three-dimensional memory array | Apr 10, 2005 | Issued |
Array
(
[id] => 7134724
[patent_doc_number] => 20050180246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'High speed DRAM architecture with uniform access latency'
[patent_app_type] => utility
[patent_app_number] => 11/101413
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7770
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0180/20050180246.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101413
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101413 | High speed DRAM architecture with uniform access latency | Apr 7, 2005 | Issued |
Array
(
[id] => 6924569
[patent_doc_number] => 20050237824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-27
[patent_title] => 'Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same'
[patent_app_type] => utility
[patent_app_number] => 11/087576
[patent_app_country] => US
[patent_app_date] => 2005-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 39
[patent_no_of_words] => 18291
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0237/20050237824.pdf
[firstpage_image] =>[orig_patent_app_number] => 11087576
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/087576 | Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same | Mar 23, 2005 | Issued |
Array
(
[id] => 7604360
[patent_doc_number] => 07116575
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-03
[patent_title] => 'Architectures for CPP ring shaped (RS) devices'
[patent_app_type] => utility
[patent_app_number] => 11/087414
[patent_app_country] => US
[patent_app_date] => 2005-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 11138
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/116/07116575.pdf
[firstpage_image] =>[orig_patent_app_number] => 11087414
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/087414 | Architectures for CPP ring shaped (RS) devices | Mar 22, 2005 | Issued |
Array
(
[id] => 409889
[patent_doc_number] => 07286391
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-23
[patent_title] => 'Semiconductor memory device capable of controlling potential level of power supply line and/or ground line'
[patent_app_type] => utility
[patent_app_number] => 11/086345
[patent_app_country] => US
[patent_app_date] => 2005-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 38
[patent_no_of_words] => 22528
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/286/07286391.pdf
[firstpage_image] =>[orig_patent_app_number] => 11086345
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086345 | Semiconductor memory device capable of controlling potential level of power supply line and/or ground line | Mar 22, 2005 | Issued |
Array
(
[id] => 5900525
[patent_doc_number] => 20060044874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/086444
[patent_app_country] => US
[patent_app_date] => 2005-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7276
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20060044874.pdf
[firstpage_image] =>[orig_patent_app_number] => 11086444
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086444 | Semiconductor memory device | Mar 22, 2005 | Issued |
Array
(
[id] => 5698783
[patent_doc_number] => 20060215467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-28
[patent_title] => 'Method of increasing data setup and hold margin in case of non-symmetrical PVT'
[patent_app_type] => utility
[patent_app_number] => 11/087182
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4095
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20060215467.pdf
[firstpage_image] =>[orig_patent_app_number] => 11087182
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/087182 | Method of increasing data setup and hold margin in case of non-symmetrical PVT | Mar 21, 2005 | Abandoned |
Array
(
[id] => 617891
[patent_doc_number] => 07145824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-05
[patent_title] => 'Temperature compensation of thin film diode voltage threshold in memory sensing circuit'
[patent_app_type] => utility
[patent_app_number] => 11/086884
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8227
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/145/07145824.pdf
[firstpage_image] =>[orig_patent_app_number] => 11086884
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086884 | Temperature compensation of thin film diode voltage threshold in memory sensing circuit | Mar 21, 2005 | Issued |
Array
(
[id] => 7188864
[patent_doc_number] => 20050162911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-28
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/085496
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3891
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20050162911.pdf
[firstpage_image] =>[orig_patent_app_number] => 11085496
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/085496 | Nonvolatile semiconductor memory device with a plurality of sectors | Mar 21, 2005 | Issued |
Array
(
[id] => 5737352
[patent_doc_number] => 20060007742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Charge trapping non-volatile memory and method for gate-by-gate erase for same'
[patent_app_type] => utility
[patent_app_number] => 11/085458
[patent_app_country] => US
[patent_app_date] => 2005-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 15744
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20060007742.pdf
[firstpage_image] =>[orig_patent_app_number] => 11085458
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/085458 | Charge trapping non-volatile memory and method for gate-by-gate erase for same | Mar 20, 2005 | Issued |
Array
(
[id] => 5737351
[patent_doc_number] => 20060007741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same'
[patent_app_type] => utility
[patent_app_number] => 11/085326
[patent_app_country] => US
[patent_app_date] => 2005-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 15749
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20060007741.pdf
[firstpage_image] =>[orig_patent_app_number] => 11085326
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/085326 | Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same | Mar 20, 2005 | Issued |
Array
(
[id] => 5665841
[patent_doc_number] => 20060171191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Memory architecture of display device and memory writing method for the same'
[patent_app_type] => utility
[patent_app_number] => 11/082758
[patent_app_country] => US
[patent_app_date] => 2005-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5187
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20060171191.pdf
[firstpage_image] =>[orig_patent_app_number] => 11082758
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/082758 | Memory architecture of display device and memory writing method for the same | Mar 17, 2005 | Issued |
Array
(
[id] => 5654256
[patent_doc_number] => 20060139991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Magnetic memory device, method for writing magnetic memory device and method for reading magnetic memory device'
[patent_app_type] => utility
[patent_app_number] => 11/081524
[patent_app_country] => US
[patent_app_date] => 2005-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 7407
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0139/20060139991.pdf
[firstpage_image] =>[orig_patent_app_number] => 11081524
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/081524 | Magnetic memory device, method for writing magnetic memory device and method for reading magnetic memory device | Mar 16, 2005 | Issued |
Array
(
[id] => 5758661
[patent_doc_number] => 20060209606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-21
[patent_title] => 'LOW POWER DELAY CONTROLLED ZERO SENSITIVE SENSE AMPLIFIER'
[patent_app_type] => utility
[patent_app_number] => 11/081276
[patent_app_country] => US
[patent_app_date] => 2005-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 14396
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20060209606.pdf
[firstpage_image] =>[orig_patent_app_number] => 11081276
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/081276 | Low power delay controlled zero sensitive sense amplifier | Mar 15, 2005 | Issued |
Array
(
[id] => 678409
[patent_doc_number] => 07088620
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-08
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/080424
[patent_app_country] => US
[patent_app_date] => 2005-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 11913
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/088/07088620.pdf
[firstpage_image] =>[orig_patent_app_number] => 11080424
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/080424 | Nonvolatile semiconductor memory device | Mar 15, 2005 | Issued |
Array
(
[id] => 475574
[patent_doc_number] => 07230869
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-12
[patent_title] => 'Method and apparatus for accessing contents of memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/081870
[patent_app_country] => US
[patent_app_date] => 2005-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5325
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/230/07230869.pdf
[firstpage_image] =>[orig_patent_app_number] => 11081870
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/081870 | Method and apparatus for accessing contents of memory cells | Mar 14, 2005 | Issued |