Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6943583 [patent_doc_number] => 20050195632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Non-volatile memory with a single transistor and resistive memory element' [patent_app_type] => utility [patent_app_number] => 11/061101 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6289 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195632.pdf [firstpage_image] =>[orig_patent_app_number] => 11061101 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061101
Non-volatile memory with a single transistor and resistive memory element Feb 17, 2005 Issued
Array ( [id] => 399216 [patent_doc_number] => 07295463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Phase-changeable memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/055094 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 35 [patent_no_of_words] => 5637 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295463.pdf [firstpage_image] =>[orig_patent_app_number] => 11055094 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055094
Phase-changeable memory device and method of manufacturing the same Feb 10, 2005 Issued
Array ( [id] => 5671378 [patent_doc_number] => 20060176732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'SRAM and dual single ended bit sense for an SRAM' [patent_app_type] => utility [patent_app_number] => 11/055416 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3218 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20060176732.pdf [firstpage_image] =>[orig_patent_app_number] => 11055416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055416
SRAM and dual single ended bit sense for an SRAM Feb 9, 2005 Issued
Array ( [id] => 6965129 [patent_doc_number] => 20050232026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Ultraviolet erasable semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/053851 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4889 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20050232026.pdf [firstpage_image] =>[orig_patent_app_number] => 11053851 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/053851
Ultraviolet erasable semiconductor memory device Feb 9, 2005 Issued
Array ( [id] => 554490 [patent_doc_number] => 07167401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Low power chip select (CS) latency option' [patent_app_type] => utility [patent_app_number] => 11/055332 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 25 [patent_no_of_words] => 7608 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167401.pdf [firstpage_image] =>[orig_patent_app_number] => 11055332 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055332
Low power chip select (CS) latency option Feb 9, 2005 Issued
Array ( [id] => 665603 [patent_doc_number] => 07102946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Local bit select circuit with slow read recovery scheme' [patent_app_type] => utility [patent_app_number] => 11/054148 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102946.pdf [firstpage_image] =>[orig_patent_app_number] => 11054148 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054148
Local bit select circuit with slow read recovery scheme Feb 8, 2005 Issued
Array ( [id] => 682512 [patent_doc_number] => 07085173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-01 [patent_title] => 'Write driver circuit for memory array' [patent_app_type] => utility [patent_app_number] => 11/054270 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2366 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085173.pdf [firstpage_image] =>[orig_patent_app_number] => 11054270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054270
Write driver circuit for memory array Feb 8, 2005 Issued
Array ( [id] => 652232 [patent_doc_number] => 07113433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Local bit select with suppression of fast read before write' [patent_app_type] => utility [patent_app_number] => 11/054402 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3440 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113433.pdf [firstpage_image] =>[orig_patent_app_number] => 11054402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054402
Local bit select with suppression of fast read before write Feb 8, 2005 Issued
Array ( [id] => 704715 [patent_doc_number] => 07064990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method and apparatus for implementing multiple column redundancy for memory' [patent_app_type] => utility [patent_app_number] => 11/053812 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3936 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064990.pdf [firstpage_image] =>[orig_patent_app_number] => 11053812 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/053812
Method and apparatus for implementing multiple column redundancy for memory Feb 8, 2005 Issued
Array ( [id] => 5671379 [patent_doc_number] => 20060176733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Method of switching an MRAM cell comprising bidirectional current generation' [patent_app_type] => utility [patent_app_number] => 11/054112 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5936 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20060176733.pdf [firstpage_image] =>[orig_patent_app_number] => 11054112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054112
Method of switching an MRAM cell comprising bidirectional current generation Feb 8, 2005 Issued
Array ( [id] => 5671406 [patent_doc_number] => 20060176760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'GLOBAL AND LOCAL READ CONTROL SYNCHRONIZATION METHOD AND SYSTEM FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS' [patent_app_type] => utility [patent_app_number] => 11/054176 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3238 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20060176760.pdf [firstpage_image] =>[orig_patent_app_number] => 11054176 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054176
Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays Feb 8, 2005 Issued
Array ( [id] => 701796 [patent_doc_number] => 07068554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-27 [patent_title] => 'Apparatus and method for implementing multiple memory redundancy with delay tracking clock' [patent_app_type] => utility [patent_app_number] => 11/054272 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2759 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/068/07068554.pdf [firstpage_image] =>[orig_patent_app_number] => 11054272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054272
Apparatus and method for implementing multiple memory redundancy with delay tracking clock Feb 8, 2005 Issued
Array ( [id] => 5671393 [patent_doc_number] => 20060176747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Circuit for interfacing local bitlines with global bitline' [patent_app_type] => utility [patent_app_number] => 11/054296 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2434 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20060176747.pdf [firstpage_image] =>[orig_patent_app_number] => 11054296 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054296
Circuit for interfacing local bitlines with global bitline Feb 8, 2005 Abandoned
Array ( [id] => 6911104 [patent_doc_number] => 20050174862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Semiconductor memory device and method of testing semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/051346 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9587 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20050174862.pdf [firstpage_image] =>[orig_patent_app_number] => 11051346 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051346
Semiconductor memory device and method of testing semiconductor memory device Feb 3, 2005 Issued
Array ( [id] => 471282 [patent_doc_number] => 07233518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-19 [patent_title] => 'Radiation-hardened SRAM cell with write error protection' [patent_app_type] => utility [patent_app_number] => 11/051916 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/233/07233518.pdf [firstpage_image] =>[orig_patent_app_number] => 11051916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051916
Radiation-hardened SRAM cell with write error protection Feb 3, 2005 Issued
Array ( [id] => 7170314 [patent_doc_number] => 20050122246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Sense amplifier with adaptive reference generation' [patent_app_type] => utility [patent_app_number] => 11/042006 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1691 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122246.pdf [firstpage_image] =>[orig_patent_app_number] => 11042006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042006
Sense amplifier with adaptive reference generation Jan 24, 2005 Issued
Array ( [id] => 426301 [patent_doc_number] => 07272061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Dynamic pre-charge level control in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/041345 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6320 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272061.pdf [firstpage_image] =>[orig_patent_app_number] => 11041345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/041345
Dynamic pre-charge level control in semiconductor devices Jan 23, 2005 Issued
Array ( [id] => 652200 [patent_doc_number] => 07113420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Molecular memory cell' [patent_app_type] => utility [patent_app_number] => 11/034078 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113420.pdf [firstpage_image] =>[orig_patent_app_number] => 11034078 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034078
Molecular memory cell Jan 11, 2005 Issued
Array ( [id] => 661109 [patent_doc_number] => 07106617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Ferroelectric memory devices having a plate line control circuit and methods for operating the same' [patent_app_type] => utility [patent_app_number] => 11/029616 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6997 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106617.pdf [firstpage_image] =>[orig_patent_app_number] => 11029616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029616
Ferroelectric memory devices having a plate line control circuit and methods for operating the same Jan 4, 2005 Issued
Array ( [id] => 678371 [patent_doc_number] => 07088603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'DRAM CAM memory' [patent_app_type] => utility [patent_app_number] => 11/010574 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2805 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088603.pdf [firstpage_image] =>[orig_patent_app_number] => 11010574 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/010574
DRAM CAM memory Dec 13, 2004 Issued
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