Son Luu Mai

Array ( [id] => 665603 [patent_doc_number] => 07102946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Local bit select circuit with slow read recovery scheme' [patent_app_type] => utility [patent_app_number] => 11/054148 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102946.pdf [firstpage_image] =>[orig_patent_app_number] => 11054148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 471282 [patent_doc_number] => 07233518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-19 [patent_title] => 'Radiation-hardened SRAM cell with write error protection' [patent_app_type] => utility [patent_app_number] => 11/051916 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/233/07233518.pdf [firstpage_image] =>[orig_patent_app_number] => 11051916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6911104 [patent_doc_number] => 20050174862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Semiconductor memory device and method of testing semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/051346 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9587 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20050174862.pdf [firstpage_image] =>[orig_patent_app_number] => 11051346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7170314 [patent_doc_number] => 20050122246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Sense amplifier with adaptive reference generation' [patent_app_type] => utility [patent_app_number] => 11/042006 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1691 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122246.pdf [firstpage_image] =>[orig_patent_app_number] => 11042006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 426301 [patent_doc_number] => 07272061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Dynamic pre-charge level control in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/041345 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6320 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272061.pdf [firstpage_image] =>[orig_patent_app_number] => 11041345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 652200 [patent_doc_number] => 07113420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Molecular memory cell' [patent_app_type] => utility [patent_app_number] => 11/034078 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113420.pdf [firstpage_image] =>[orig_patent_app_number] => 11034078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 661109 [patent_doc_number] => 07106617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Ferroelectric memory devices having a plate line control circuit and methods for operating the same' [patent_app_type] => utility [patent_app_number] => 11/029616 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6997 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106617.pdf [firstpage_image] =>[orig_patent_app_number] => 11029616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 678371 [patent_doc_number] => 07088603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'DRAM CAM memory' [patent_app_type] => utility [patent_app_number] => 11/010574 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2805 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088603.pdf [firstpage_image] =>[orig_patent_app_number] => 11010574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 842124 [patent_doc_number] => 07391640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => '2-transistor floating-body dram' [patent_app_type] => utility [patent_app_number] => 11/008666 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5603 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391640.pdf [firstpage_image] =>[orig_patent_app_number] => 11008666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5624084 [patent_doc_number] => 20060262589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Semiconductor integrated circuit, operating method thereof, and ic card including the circuit' [patent_app_type] => utility [patent_app_number] => 10/555964 [patent_app_country] => US [patent_app_date] => 2004-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4791 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20060262589.pdf [firstpage_image] =>[orig_patent_app_number] => 10555964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 342498 [patent_doc_number] => 07502256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Systems and methods for reducing unauthorized data recovery from solid-state storage devices' [patent_app_type] => utility [patent_app_number] => 11/000134 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6478 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502256.pdf [firstpage_image] =>[orig_patent_app_number] => 11000134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5187142 [patent_doc_number] => 20070165450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Data retention indicator for magnetic memories' [patent_app_type] => utility [patent_app_number] => 10/579934 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6092 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165450.pdf [firstpage_image] =>[orig_patent_app_number] => 10579934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7038096 [patent_doc_number] => 20050157530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Ferroelectric memory' [patent_app_type] => utility [patent_app_number] => 10/973832 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10709 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20050157530.pdf [firstpage_image] =>[orig_patent_app_number] => 10973832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7156889 [patent_doc_number] => 20050083726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Soft errors handling EEPROM devices' [patent_app_type] => utility [patent_app_number] => 10/974366 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7569 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083726.pdf [firstpage_image] =>[orig_patent_app_number] => 10974366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4548606 [patent_doc_number] => 07876605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Phase change memory, phase change memory assembly, phase change memory cell, 2D phase change memory cell array, 3D phase change memory cell array and electronic component' [patent_app_type] => utility [patent_app_number] => 10/576760 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 11093 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/876/07876605.pdf [firstpage_image] =>[orig_patent_app_number] => 10576760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 947188 [patent_doc_number] => 06965523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Multilevel memory device with memory cells storing non-power of two voltage levels' [patent_app_type] => utility [patent_app_number] => 10/964160 [patent_app_country] => US [patent_app_date] => 2004-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3026 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965523.pdf [firstpage_image] =>[orig_patent_app_number] => 10964160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6937703 [patent_doc_number] => 20050111264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Flash memory device' [patent_app_type] => utility [patent_app_number] => 10/954255 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4635 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20050111264.pdf [firstpage_image] =>[orig_patent_app_number] => 10954255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 657236 [patent_doc_number] => 07110278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Crosspoint memory array utilizing one time programmable antifuse cells' [patent_app_type] => utility [patent_app_number] => 10/954537 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2703 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/110/07110278.pdf [firstpage_image] =>[orig_patent_app_number] => 10954537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 422666 [patent_doc_number] => 07274601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Programming and erasing method for charge-trapping memory devices' [patent_app_type] => utility [patent_app_number] => 10/951999 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2920 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274601.pdf [firstpage_image] =>[orig_patent_app_number] => 10951999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 308458 [patent_doc_number] => 07532536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/577398 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 51 [patent_no_of_words] => 15324 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/532/07532536.pdf [firstpage_image] =>[orig_patent_app_number] => 10577398 [rel_patent_id] =>[rel_patent_doc_number] =>)