Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 842124 [patent_doc_number] => 07391640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => '2-transistor floating-body dram' [patent_app_type] => utility [patent_app_number] => 11/008666 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5603 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391640.pdf [firstpage_image] =>[orig_patent_app_number] => 11008666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008666
2-transistor floating-body dram Dec 9, 2004 Issued
Array ( [id] => 5624084 [patent_doc_number] => 20060262589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Semiconductor integrated circuit, operating method thereof, and ic card including the circuit' [patent_app_type] => utility [patent_app_number] => 10/555964 [patent_app_country] => US [patent_app_date] => 2004-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4791 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20060262589.pdf [firstpage_image] =>[orig_patent_app_number] => 10555964 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/555964
Semiconductor integrated circuit, operating method thereof, and IC card including the circuit Dec 6, 2004 Issued
Array ( [id] => 342498 [patent_doc_number] => 07502256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Systems and methods for reducing unauthorized data recovery from solid-state storage devices' [patent_app_type] => utility [patent_app_number] => 11/000134 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6478 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502256.pdf [firstpage_image] =>[orig_patent_app_number] => 11000134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000134
Systems and methods for reducing unauthorized data recovery from solid-state storage devices Nov 29, 2004 Issued
Array ( [id] => 5187142 [patent_doc_number] => 20070165450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Data retention indicator for magnetic memories' [patent_app_type] => utility [patent_app_number] => 10/579934 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6092 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165450.pdf [firstpage_image] =>[orig_patent_app_number] => 10579934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/579934
Data retention indicator for magnetic memories Nov 8, 2004 Issued
Array ( [id] => 7038096 [patent_doc_number] => 20050157530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Ferroelectric memory' [patent_app_type] => utility [patent_app_number] => 10/973832 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10709 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20050157530.pdf [firstpage_image] =>[orig_patent_app_number] => 10973832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973832
Ferroelectric memory Oct 26, 2004 Issued
Array ( [id] => 7156889 [patent_doc_number] => 20050083726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Soft errors handling EEPROM devices' [patent_app_type] => utility [patent_app_number] => 10/974366 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7569 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083726.pdf [firstpage_image] =>[orig_patent_app_number] => 10974366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974366
Soft errors handling in EEPROM devices Oct 25, 2004 Issued
Array ( [id] => 4548606 [patent_doc_number] => 07876605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Phase change memory, phase change memory assembly, phase change memory cell, 2D phase change memory cell array, 3D phase change memory cell array and electronic component' [patent_app_type] => utility [patent_app_number] => 10/576760 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 11093 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/876/07876605.pdf [firstpage_image] =>[orig_patent_app_number] => 10576760 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/576760
Phase change memory, phase change memory assembly, phase change memory cell, 2D phase change memory cell array, 3D phase change memory cell array and electronic component Oct 18, 2004 Issued
Array ( [id] => 947188 [patent_doc_number] => 06965523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Multilevel memory device with memory cells storing non-power of two voltage levels' [patent_app_type] => utility [patent_app_number] => 10/964160 [patent_app_country] => US [patent_app_date] => 2004-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3026 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965523.pdf [firstpage_image] =>[orig_patent_app_number] => 10964160 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/964160
Multilevel memory device with memory cells storing non-power of two voltage levels Oct 11, 2004 Issued
Array ( [id] => 657236 [patent_doc_number] => 07110278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Crosspoint memory array utilizing one time programmable antifuse cells' [patent_app_type] => utility [patent_app_number] => 10/954537 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2703 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/110/07110278.pdf [firstpage_image] =>[orig_patent_app_number] => 10954537 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954537
Crosspoint memory array utilizing one time programmable antifuse cells Sep 28, 2004 Issued
Array ( [id] => 6937703 [patent_doc_number] => 20050111264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Flash memory device' [patent_app_type] => utility [patent_app_number] => 10/954255 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4635 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20050111264.pdf [firstpage_image] =>[orig_patent_app_number] => 10954255 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954255
Flash memory device Sep 28, 2004 Issued
Array ( [id] => 422666 [patent_doc_number] => 07274601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Programming and erasing method for charge-trapping memory devices' [patent_app_type] => utility [patent_app_number] => 10/951999 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2920 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274601.pdf [firstpage_image] =>[orig_patent_app_number] => 10951999 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/951999
Programming and erasing method for charge-trapping memory devices Sep 26, 2004 Issued
Array ( [id] => 308458 [patent_doc_number] => 07532536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/577398 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 51 [patent_no_of_words] => 15324 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/532/07532536.pdf [firstpage_image] =>[orig_patent_app_number] => 10577398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/577398
Semiconductor memory device Sep 16, 2004 Issued
Array ( [id] => 391233 [patent_doc_number] => 07301831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Memory systems with variable delays for write data signals' [patent_app_type] => utility [patent_app_number] => 10/942225 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11482 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301831.pdf [firstpage_image] =>[orig_patent_app_number] => 10942225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/942225
Memory systems with variable delays for write data signals Sep 14, 2004 Issued
Array ( [id] => 7032277 [patent_doc_number] => 20050030786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Low remanence flux concentrator for MRAM devices' [patent_app_type] => utility [patent_app_number] => 10/932949 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8611 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20050030786.pdf [firstpage_image] =>[orig_patent_app_number] => 10932949 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932949
Low remanence flux concentrator for MRAM devices Sep 1, 2004 Issued
Array ( [id] => 791367 [patent_doc_number] => 06985393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => utility [patent_app_number] => 10/928400 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3311 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/985/06985393.pdf [firstpage_image] =>[orig_patent_app_number] => 10928400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928400
Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines Aug 26, 2004 Issued
Array ( [id] => 954528 [patent_doc_number] => 06958945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Device having a memory array storing each bit in multiple memory cells' [patent_app_type] => utility [patent_app_number] => 10/928380 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8242 [patent_no_of_claims] => 97 [patent_no_of_ind_claims] => 53 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958945.pdf [firstpage_image] =>[orig_patent_app_number] => 10928380 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928380
Device having a memory array storing each bit in multiple memory cells Aug 26, 2004 Issued
Array ( [id] => 7196293 [patent_doc_number] => 20050041502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory' [patent_app_type] => utility [patent_app_number] => 10/920206 [patent_app_country] => US [patent_app_date] => 2004-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5194 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041502.pdf [firstpage_image] =>[orig_patent_app_number] => 10920206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920206
Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory Aug 17, 2004 Issued
Array ( [id] => 621695 [patent_doc_number] => 07142462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Input signal receiving device of semiconductor memory unit' [patent_app_type] => utility [patent_app_number] => 10/919370 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4399 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/142/07142462.pdf [firstpage_image] =>[orig_patent_app_number] => 10919370 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/919370
Input signal receiving device of semiconductor memory unit Aug 16, 2004 Issued
Array ( [id] => 644084 [patent_doc_number] => 07123504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Semiconductor integrated circuit device having static random access memory mounted thereon' [patent_app_type] => utility [patent_app_number] => 10/918642 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5796 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 490 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123504.pdf [firstpage_image] =>[orig_patent_app_number] => 10918642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918642
Semiconductor integrated circuit device having static random access memory mounted thereon Aug 15, 2004 Issued
Array ( [id] => 7196175 [patent_doc_number] => 20050041477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Flash memory devices including multiple dummy cell array regions and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 10/918966 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7551 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041477.pdf [firstpage_image] =>[orig_patent_app_number] => 10918966 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918966
Methods of fabricating flash memory devices including multiple dummy cell array regions Aug 15, 2004 Issued
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