Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 391233 [patent_doc_number] => 07301831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Memory systems with variable delays for write data signals' [patent_app_type] => utility [patent_app_number] => 10/942225 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11482 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301831.pdf [firstpage_image] =>[orig_patent_app_number] => 10942225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/942225
Memory systems with variable delays for write data signals Sep 14, 2004 Issued
Array ( [id] => 7032277 [patent_doc_number] => 20050030786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Low remanence flux concentrator for MRAM devices' [patent_app_type] => utility [patent_app_number] => 10/932949 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8611 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20050030786.pdf [firstpage_image] =>[orig_patent_app_number] => 10932949 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932949
Low remanence flux concentrator for MRAM devices Sep 1, 2004 Issued
Array ( [id] => 954528 [patent_doc_number] => 06958945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Device having a memory array storing each bit in multiple memory cells' [patent_app_type] => utility [patent_app_number] => 10/928380 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8242 [patent_no_of_claims] => 97 [patent_no_of_ind_claims] => 53 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958945.pdf [firstpage_image] =>[orig_patent_app_number] => 10928380 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928380
Device having a memory array storing each bit in multiple memory cells Aug 26, 2004 Issued
Array ( [id] => 791367 [patent_doc_number] => 06985393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => utility [patent_app_number] => 10/928400 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3311 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/985/06985393.pdf [firstpage_image] =>[orig_patent_app_number] => 10928400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928400
Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines Aug 26, 2004 Issued
Array ( [id] => 7196293 [patent_doc_number] => 20050041502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory' [patent_app_type] => utility [patent_app_number] => 10/920206 [patent_app_country] => US [patent_app_date] => 2004-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5194 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041502.pdf [firstpage_image] =>[orig_patent_app_number] => 10920206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920206
Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory Aug 17, 2004 Issued
Array ( [id] => 621695 [patent_doc_number] => 07142462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Input signal receiving device of semiconductor memory unit' [patent_app_type] => utility [patent_app_number] => 10/919370 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4399 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/142/07142462.pdf [firstpage_image] =>[orig_patent_app_number] => 10919370 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/919370
Input signal receiving device of semiconductor memory unit Aug 16, 2004 Issued
Array ( [id] => 644084 [patent_doc_number] => 07123504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Semiconductor integrated circuit device having static random access memory mounted thereon' [patent_app_type] => utility [patent_app_number] => 10/918642 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5796 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 490 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123504.pdf [firstpage_image] =>[orig_patent_app_number] => 10918642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918642
Semiconductor integrated circuit device having static random access memory mounted thereon Aug 15, 2004 Issued
Array ( [id] => 5797897 [patent_doc_number] => 20060034136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Using redundant memory for extra features' [patent_app_type] => utility [patent_app_number] => 10/918894 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5137 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20060034136.pdf [firstpage_image] =>[orig_patent_app_number] => 10918894 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918894
Using redundant memory for extra features Aug 15, 2004 Issued
Array ( [id] => 7196175 [patent_doc_number] => 20050041477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Flash memory devices including multiple dummy cell array regions and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 10/918966 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7551 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041477.pdf [firstpage_image] =>[orig_patent_app_number] => 10918966 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918966
Methods of fabricating flash memory devices including multiple dummy cell array regions Aug 15, 2004 Issued
Array ( [id] => 6904479 [patent_doc_number] => 20050099874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/918356 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3273 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20050099874.pdf [firstpage_image] =>[orig_patent_app_number] => 10918356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918356
Semiconductor integrated circuit device having memory cells divided into groups Aug 15, 2004 Issued
Array ( [id] => 610323 [patent_doc_number] => 07151709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-19 [patent_title] => 'Memory device and method having programmable address configurations' [patent_app_type] => utility [patent_app_number] => 10/920716 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5805 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151709.pdf [firstpage_image] =>[orig_patent_app_number] => 10920716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920716
Memory device and method having programmable address configurations Aug 15, 2004 Issued
Array ( [id] => 7081840 [patent_doc_number] => 20050047220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/917308 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11884 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20050047220.pdf [firstpage_image] =>[orig_patent_app_number] => 10917308 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917308
Semiconductor memory device Aug 12, 2004 Issued
Array ( [id] => 7165135 [patent_doc_number] => 20050201168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/916524 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20050201168.pdf [firstpage_image] =>[orig_patent_app_number] => 10916524 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916524
Semiconductor memory device Aug 11, 2004 Issued
Array ( [id] => 5797843 [patent_doc_number] => 20060034122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Dynamic matching of signal path and reference path for sensing' [patent_app_type] => utility [patent_app_number] => 10/916413 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3918 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20060034122.pdf [firstpage_image] =>[orig_patent_app_number] => 10916413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916413
Dynamic matching of signal path and reference path for sensing Aug 11, 2004 Issued
Array ( [id] => 674451 [patent_doc_number] => 07092298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Methods of erasing a non-volatile memory device having discrete charge trap sites' [patent_app_type] => utility [patent_app_number] => 10/916716 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4503 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/092/07092298.pdf [firstpage_image] =>[orig_patent_app_number] => 10916716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916716
Methods of erasing a non-volatile memory device having discrete charge trap sites Aug 11, 2004 Issued
Array ( [id] => 762145 [patent_doc_number] => 07016258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Semiconductor device having input/output sense amplifier for multiple sampling' [patent_app_type] => utility [patent_app_number] => 10/916179 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5382 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016258.pdf [firstpage_image] =>[orig_patent_app_number] => 10916179 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916179
Semiconductor device having input/output sense amplifier for multiple sampling Aug 10, 2004 Issued
Array ( [id] => 959426 [patent_doc_number] => 06954374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Thin film magnetic memory device including memory cells having a magnetic tunnel junction' [patent_app_type] => utility [patent_app_number] => 10/915447 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 60 [patent_no_of_words] => 23561 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954374.pdf [firstpage_image] =>[orig_patent_app_number] => 10915447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915447
Thin film magnetic memory device including memory cells having a magnetic tunnel junction Aug 10, 2004 Issued
Array ( [id] => 776006 [patent_doc_number] => 07002838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 10/914084 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7556 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002838.pdf [firstpage_image] =>[orig_patent_app_number] => 10914084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914084
Semiconductor storage device Aug 9, 2004 Issued
Array ( [id] => 6970678 [patent_doc_number] => 20050036388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Method and apparatus for increasing data read speed in a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/915036 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1951 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20050036388.pdf [firstpage_image] =>[orig_patent_app_number] => 10915036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915036
Method and apparatus for increasing data read speed in a semiconductor memory device Aug 9, 2004 Issued
Array ( [id] => 7237550 [patent_doc_number] => 20050270882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'High voltage generators having an integrated discharge path for use in non-volatile semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 10/915294 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20050270882.pdf [firstpage_image] =>[orig_patent_app_number] => 10915294 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915294
High voltage generators having an integrated discharge path for use in non-volatile semiconductor memory devices Aug 9, 2004 Issued
Menu