Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7237370 [patent_doc_number] => 20050270850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Nonvolatile flash memory and method of operating the same' [patent_app_type] => utility [patent_app_number] => 10/861392 [patent_app_country] => US [patent_app_date] => 2004-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3789 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20050270850.pdf [firstpage_image] =>[orig_patent_app_number] => 10861392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861392
Nonvolatile flash memory and method of operating the same Jun 6, 2004 Issued
Array ( [id] => 772032 [patent_doc_number] => 07006393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Method and apparatus for semiconductor device repair with reduced number of programmable elements' [patent_app_type] => utility [patent_app_number] => 10/862284 [patent_app_country] => US [patent_app_date] => 2004-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6568 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/006/07006393.pdf [firstpage_image] =>[orig_patent_app_number] => 10862284 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/862284
Method and apparatus for semiconductor device repair with reduced number of programmable elements Jun 6, 2004 Issued
Array ( [id] => 772036 [patent_doc_number] => 07006394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Apparatus and method for semiconductor device repair with reduced number of programmable elements' [patent_app_type] => utility [patent_app_number] => 10/862532 [patent_app_country] => US [patent_app_date] => 2004-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5808 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/006/07006394.pdf [firstpage_image] =>[orig_patent_app_number] => 10862532 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/862532
Apparatus and method for semiconductor device repair with reduced number of programmable elements Jun 6, 2004 Issued
Array ( [id] => 7237549 [patent_doc_number] => 20050270881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'SPEEDING UP THE POWER-UP PROCEDURE FOR LOW POWER RAM' [patent_app_type] => utility [patent_app_number] => 10/861162 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2887 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20050270881.pdf [firstpage_image] =>[orig_patent_app_number] => 10861162 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861162
Speeding up the power-up procedure for low power RAM Jun 3, 2004 Issued
Array ( [id] => 741583 [patent_doc_number] => 07035164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Semiconductor memory device with a bypass circuit for verifying the characteristics of an internal clock signal' [patent_app_type] => utility [patent_app_number] => 10/861038 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7320 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035164.pdf [firstpage_image] =>[orig_patent_app_number] => 10861038 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861038
Semiconductor memory device with a bypass circuit for verifying the characteristics of an internal clock signal Jun 3, 2004 Issued
Array ( [id] => 7367993 [patent_doc_number] => 20040218437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Semiconductor device that enables simultaneous read and write/read operation' [patent_app_type] => new [patent_app_number] => 10/860275 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 20861 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20040218437.pdf [firstpage_image] =>[orig_patent_app_number] => 10860275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/860275
Semiconductor device that enables simultaneous read and write/read operation Jun 3, 2004 Issued
Array ( [id] => 768594 [patent_doc_number] => 07009887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method of determining voltage compensation for flash memory devices' [patent_app_type] => utility [patent_app_number] => 10/860450 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6864 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009887.pdf [firstpage_image] =>[orig_patent_app_number] => 10860450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/860450
Method of determining voltage compensation for flash memory devices Jun 2, 2004 Issued
Array ( [id] => 718882 [patent_doc_number] => 07054191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'Method and system for writing data to memory cells' [patent_app_type] => utility [patent_app_number] => 10/860194 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2967 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/054/07054191.pdf [firstpage_image] =>[orig_patent_app_number] => 10860194 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/860194
Method and system for writing data to memory cells Jun 2, 2004 Issued
Array ( [id] => 7415630 [patent_doc_number] => 20040264272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method and apparatus for accelerating signal equalization between a pair of signal lines' [patent_app_type] => new [patent_app_number] => 10/855410 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20040264272.pdf [firstpage_image] =>[orig_patent_app_number] => 10855410 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/855410
Method and apparatus for accelerating signal equalization between a pair of signal lines May 27, 2004 Abandoned
Array ( [id] => 768631 [patent_doc_number] => 07009903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Sense amplifying magnetic tunnel device' [patent_app_type] => utility [patent_app_number] => 10/855042 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6691 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009903.pdf [firstpage_image] =>[orig_patent_app_number] => 10855042 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/855042
Sense amplifying magnetic tunnel device May 26, 2004 Issued
Array ( [id] => 7293515 [patent_doc_number] => 20040213065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Sense amplifier with adaptive reference generation' [patent_app_type] => new [patent_app_number] => 10/853798 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1712 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213065.pdf [firstpage_image] =>[orig_patent_app_number] => 10853798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853798
Sense amplifier with adaptive reference generation May 25, 2004 Issued
Array ( [id] => 7087737 [patent_doc_number] => 20050007849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'DRAM memory circuit with sense amplifiers' [patent_app_type] => utility [patent_app_number] => 10/850185 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007849.pdf [firstpage_image] =>[orig_patent_app_number] => 10850185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/850185
DRAM memory circuit with sense amplifiers May 19, 2004 Issued
Array ( [id] => 723426 [patent_doc_number] => 07050337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Writing control method and writing control system of semiconductor storage device, and portable electronic apparatus' [patent_app_type] => utility [patent_app_number] => 10/848082 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 23451 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/050/07050337.pdf [firstpage_image] =>[orig_patent_app_number] => 10848082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/848082
Writing control method and writing control system of semiconductor storage device, and portable electronic apparatus May 18, 2004 Issued
Array ( [id] => 7244207 [patent_doc_number] => 20040257889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Clock generation circuit and semiconductor memory device using the same' [patent_app_type] => new [patent_app_number] => 10/845082 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3899 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257889.pdf [firstpage_image] =>[orig_patent_app_number] => 10845082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/845082
Clock generation circuit and semiconductor memory device using the same May 13, 2004 Issued
Array ( [id] => 749389 [patent_doc_number] => 07027332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Memory I/O driving circuit with reduced noise and driving method' [patent_app_type] => utility [patent_app_number] => 10/846746 [patent_app_country] => US [patent_app_date] => 2004-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3126 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/027/07027332.pdf [firstpage_image] =>[orig_patent_app_number] => 10846746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/846746
Memory I/O driving circuit with reduced noise and driving method May 12, 2004 Issued
Array ( [id] => 7274286 [patent_doc_number] => 20040233737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Circuit arrangement and method for setting a voltage supply for a read/write amplifier of an integrated memory' [patent_app_type] => new [patent_app_number] => 10/841546 [patent_app_country] => US [patent_app_date] => 2004-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2985 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233737.pdf [firstpage_image] =>[orig_patent_app_number] => 10841546 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841546
Circuit arrangement and method for setting a voltage supply for a read/write amplifier of an integrated memory May 9, 2004 Issued
Array ( [id] => 791365 [patent_doc_number] => 06985391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'High speed redundant data sensing method and apparatus' [patent_app_type] => utility [patent_app_number] => 10/841144 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5002 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/985/06985391.pdf [firstpage_image] =>[orig_patent_app_number] => 10841144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841144
High speed redundant data sensing method and apparatus May 6, 2004 Issued
Array ( [id] => 7606498 [patent_doc_number] => 07099221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Memory controller method and system compensating for memory cell data losses' [patent_app_type] => utility [patent_app_number] => 10/839942 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5000 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/099/07099221.pdf [firstpage_image] =>[orig_patent_app_number] => 10839942 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/839942
Memory controller method and system compensating for memory cell data losses May 5, 2004 Issued
Array ( [id] => 7044414 [patent_doc_number] => 20050249009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Efficient refresh operation for semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 10/839048 [patent_app_country] => US [patent_app_date] => 2004-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3257 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20050249009.pdf [firstpage_image] =>[orig_patent_app_number] => 10839048 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/839048
Efficient refresh operation for semiconductor memory devices May 4, 2004 Issued
Array ( [id] => 7243890 [patent_doc_number] => 20040257846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Nonvolatile semiconductor memory with X8/X16 operation mode using address control' [patent_app_type] => new [patent_app_number] => 10/835148 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4622 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257846.pdf [firstpage_image] =>[orig_patent_app_number] => 10835148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/835148
Nonvolatile semiconductor memory with X8/X16 operation mode using address control Apr 27, 2004 Issued
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