Son Luu Mai

Array ( [id] => 7179587 [patent_doc_number] => 20040202264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Multi-frequency synchronizing clock signal generator' [patent_app_type] => new [patent_app_number] => 10/835361 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7915 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20040202264.pdf [firstpage_image] =>[orig_patent_app_number] => 10835361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7179585 [patent_doc_number] => 20040202263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Multi-frequency synchronizing clock signal generator' [patent_app_type] => new [patent_app_number] => 10/835360 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7883 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20040202263.pdf [firstpage_image] =>[orig_patent_app_number] => 10835360 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1067344 [patent_doc_number] => 06847534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'High density dynamic ternary-CAM memory architecture' [patent_app_type] => utility [patent_app_number] => 10/833306 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3122 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/847/06847534.pdf [firstpage_image] =>[orig_patent_app_number] => 10833306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7096322 [patent_doc_number] => 20050128780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/830046 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9107 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20050128780.pdf [firstpage_image] =>[orig_patent_app_number] => 10830046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 961663 [patent_doc_number] => 06952377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Memory device and method for writing data in memory cell with boosted bitline voltage' [patent_app_type] => utility [patent_app_number] => 10/824784 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2559 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952377.pdf [firstpage_image] =>[orig_patent_app_number] => 10824784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7315811 [patent_doc_number] => 20040223365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Semiconductor device and method for inputting/outputting data simultaneously through single pad' [patent_app_type] => new [patent_app_number] => 10/819678 [patent_app_country] => US [patent_app_date] => 2004-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4235 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20040223365.pdf [firstpage_image] =>[orig_patent_app_number] => 10819678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5203671 [patent_doc_number] => 20070025150 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2007-02-01 [patent_title] => 'FLASH MEMORY DEVICE CAPABLE OF PREVENTING PROGRAM DISTURBANCE ACCORDING TO PARTIAL PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 10/819385 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6336 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A9/0025/20070025150.pdf [firstpage_image] =>[orig_patent_app_number] => 10819385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5203671 [patent_doc_number] => 20070025150 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2007-02-01 [patent_title] => 'FLASH MEMORY DEVICE CAPABLE OF PREVENTING PROGRAM DISTURBANCE ACCORDING TO PARTIAL PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 10/819385 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6336 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A9/0025/20070025150.pdf [firstpage_image] =>[orig_patent_app_number] => 10819385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6950940 [patent_doc_number] => 20050226034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Resistance change sensor' [patent_app_type] => utility [patent_app_number] => 10/816482 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5096 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20050226034.pdf [firstpage_image] =>[orig_patent_app_number] => 10816482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7102640 [patent_doc_number] => 20050105366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method for detecting and preventing tampering with one-time programmable digital devices' [patent_app_type] => utility [patent_app_number] => 10/815348 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20050105366.pdf [firstpage_image] =>[orig_patent_app_number] => 10815348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547300 [patent_doc_number] => 07177182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Rewriteable electronic fuses' [patent_app_type] => utility [patent_app_number] => 10/814868 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 37 [patent_no_of_words] => 13930 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177182.pdf [firstpage_image] =>[orig_patent_app_number] => 10814868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 693387 [patent_doc_number] => 07075835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Redundancy control circuit which surely programs program elements and semiconductor memory using the same' [patent_app_type] => utility [patent_app_number] => 10/809044 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11815 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075835.pdf [firstpage_image] =>[orig_patent_app_number] => 10809044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 144208 [patent_doc_number] => 07688643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Device and method for controlling solid-state memory system' [patent_app_type] => utility [patent_app_number] => 10/809061 [patent_app_country] => US [patent_app_date] => 2004-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9653 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/688/07688643.pdf [firstpage_image] =>[orig_patent_app_number] => 10809061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7293491 [patent_doc_number] => 20040213050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/806417 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6584 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213050.pdf [firstpage_image] =>[orig_patent_app_number] => 10806417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 631858 [patent_doc_number] => 07133304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Method and apparatus to reduce storage node disturbance in ferroelectric memory' [patent_app_type] => utility [patent_app_number] => 10/805809 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9517 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/133/07133304.pdf [firstpage_image] =>[orig_patent_app_number] => 10805809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1019866 [patent_doc_number] => 06891772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'High speed DRAM architecture with uniform access latency' [patent_app_type] => utility [patent_app_number] => 10/804182 [patent_app_country] => US [patent_app_date] => 2004-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 7777 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891772.pdf [firstpage_image] =>[orig_patent_app_number] => 10804182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 670059 [patent_doc_number] => 07095642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-22 [patent_title] => 'Method and circuit for reducing defect current from array element failures in random access memories' [patent_app_type] => utility [patent_app_number] => 10/799742 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6205 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/095/07095642.pdf [firstpage_image] =>[orig_patent_app_number] => 10799742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 944835 [patent_doc_number] => 06967891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Information processing apparatus and semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/797178 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 11347 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967891.pdf [firstpage_image] =>[orig_patent_app_number] => 10797178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 931945 [patent_doc_number] => 06980456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Memory with low and fixed pre-charge loading' [patent_app_type] => utility [patent_app_number] => 10/794048 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3398 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/980/06980456.pdf [firstpage_image] =>[orig_patent_app_number] => 10794048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 762068 [patent_doc_number] => 07016235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Data sorting in memories' [patent_app_type] => utility [patent_app_number] => 10/794782 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 12039 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016235.pdf [firstpage_image] =>[orig_patent_app_number] => 10794782 [rel_patent_id] =>[rel_patent_doc_number] =>)