Search

Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 635951 [patent_doc_number] => 07130216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'One-device non-volatile random access memory cell' [patent_app_type] => utility [patent_app_number] => 10/788230 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6956 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/130/07130216.pdf [firstpage_image] =>[orig_patent_app_number] => 10788230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/788230
One-device non-volatile random access memory cell Feb 25, 2004 Issued
Array ( [id] => 1082839 [patent_doc_number] => 06833278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Low remanence flux concentrator for MRAM devices' [patent_app_type] => B2 [patent_app_number] => 10/785769 [patent_app_country] => US [patent_app_date] => 2004-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 36 [patent_no_of_words] => 8595 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833278.pdf [firstpage_image] =>[orig_patent_app_number] => 10785769 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785769
Low remanence flux concentrator for MRAM devices Feb 23, 2004 Issued
Array ( [id] => 7474101 [patent_doc_number] => 20040168014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Device and method for controlling solid-state memory system' [patent_app_type] => new [patent_app_number] => 10/785373 [patent_app_country] => US [patent_app_date] => 2004-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9322 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20040168014.pdf [firstpage_image] =>[orig_patent_app_number] => 10785373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785373
Device and method for controlling solid-state memory system Feb 22, 2004 Abandoned
Array ( [id] => 7608818 [patent_doc_number] => 06999373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'High speed wordline decoder for driving a long wordline' [patent_app_type] => utility [patent_app_number] => 10/777674 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2481 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/999/06999373.pdf [firstpage_image] =>[orig_patent_app_number] => 10777674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777674
High speed wordline decoder for driving a long wordline Feb 12, 2004 Issued
Array ( [id] => 7150758 [patent_doc_number] => 20050024984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Data input circuit and method for synchronous semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/771488 [patent_app_country] => US [patent_app_date] => 2004-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7470 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024984.pdf [firstpage_image] =>[orig_patent_app_number] => 10771488 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/771488
Data input circuit and method for synchronous semiconductor memory device Feb 3, 2004 Issued
Array ( [id] => 467053 [patent_doc_number] => 07239568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Current threshold detector' [patent_app_type] => utility [patent_app_number] => 10/767428 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5697 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239568.pdf [firstpage_image] =>[orig_patent_app_number] => 10767428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/767428
Current threshold detector Jan 28, 2004 Issued
Array ( [id] => 7342607 [patent_doc_number] => 20040246806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Semiconductor memory having a flexible dual-bank architecture with improved row decoding' [patent_app_type] => new [patent_app_number] => 10/768398 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9060 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246806.pdf [firstpage_image] =>[orig_patent_app_number] => 10768398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/768398
Semiconductor memory having a flexible dual-bank architecture with improved row decoding Jan 28, 2004 Issued
Array ( [id] => 682459 [patent_doc_number] => 07085149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method and apparatus for reducing leakage current in a read only memory device using transistor bias' [patent_app_type] => utility [patent_app_number] => 10/764000 [patent_app_country] => US [patent_app_date] => 2004-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3958 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085149.pdf [firstpage_image] =>[orig_patent_app_number] => 10764000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764000
Method and apparatus for reducing leakage current in a read only memory device using transistor bias Jan 22, 2004 Issued
Array ( [id] => 997863 [patent_doc_number] => 06914837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'DRAM memory with a shared sense amplifier structure' [patent_app_type] => utility [patent_app_number] => 10/761242 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914837.pdf [firstpage_image] =>[orig_patent_app_number] => 10761242 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761242
DRAM memory with a shared sense amplifier structure Jan 21, 2004 Issued
Array ( [id] => 7059859 [patent_doc_number] => 20050002219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Methods and devices for preventing data stored in memory from being read out' [patent_app_type] => utility [patent_app_number] => 10/761396 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8088 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20050002219.pdf [firstpage_image] =>[orig_patent_app_number] => 10761396 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761396
Methods and devices for preventing data stored in memory from being read out Jan 21, 2004 Issued
Array ( [id] => 944829 [patent_doc_number] => 06967885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Concurrent refresh mode with distributed row address counters in an embedded DRAM' [patent_app_type] => utility [patent_app_number] => 10/757846 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3943 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967885.pdf [firstpage_image] =>[orig_patent_app_number] => 10757846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757846
Concurrent refresh mode with distributed row address counters in an embedded DRAM Jan 14, 2004 Issued
Array ( [id] => 959431 [patent_doc_number] => 06954379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Power-on reset circuit for erasing of split gate flash memory reference cells' [patent_app_type] => utility [patent_app_number] => 10/755496 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2010 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954379.pdf [firstpage_image] =>[orig_patent_app_number] => 10755496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755496
Power-on reset circuit for erasing of split gate flash memory reference cells Jan 11, 2004 Issued
Array ( [id] => 944814 [patent_doc_number] => 06967870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Combination NAND-NOR memory device' [patent_app_type] => utility [patent_app_number] => 10/753644 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967870.pdf [firstpage_image] =>[orig_patent_app_number] => 10753644 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753644
Combination NAND-NOR memory device Jan 6, 2004 Issued
Array ( [id] => 745547 [patent_doc_number] => 07031191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Stabilization method for drain voltage in non-volatile multi-level memory cells and related memory device' [patent_app_type] => utility [patent_app_number] => 10/748701 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2536 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/031/07031191.pdf [firstpage_image] =>[orig_patent_app_number] => 10748701 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748701
Stabilization method for drain voltage in non-volatile multi-level memory cells and related memory device Dec 29, 2003 Issued
Array ( [id] => 741545 [patent_doc_number] => 07035142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Non volatile memory device including a predetermined number of sectors' [patent_app_type] => utility [patent_app_number] => 10/748696 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1697 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035142.pdf [firstpage_image] =>[orig_patent_app_number] => 10748696 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748696
Non volatile memory device including a predetermined number of sectors Dec 29, 2003 Issued
Array ( [id] => 531741 [patent_doc_number] => 07187605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 10/747400 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5543 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187605.pdf [firstpage_image] =>[orig_patent_app_number] => 10747400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747400
Semiconductor storage device Dec 29, 2003 Issued
Array ( [id] => 689022 [patent_doc_number] => 07079420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Method for operating a memory device' [patent_app_type] => utility [patent_app_number] => 10/747217 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4172 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/079/07079420.pdf [firstpage_image] =>[orig_patent_app_number] => 10747217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747217
Method for operating a memory device Dec 29, 2003 Issued
Array ( [id] => 1007162 [patent_doc_number] => 06906973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Bit-line droop reduction' [patent_app_type] => utility [patent_app_number] => 10/746148 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 1953 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906973.pdf [firstpage_image] =>[orig_patent_app_number] => 10746148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746148
Bit-line droop reduction Dec 23, 2003 Issued
Array ( [id] => 7150612 [patent_doc_number] => 20050024916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'CELL ARRAY BLOCK OF FERAM, AND FERAM USING CELL ARRAY' [patent_app_type] => utility [patent_app_number] => 10/737846 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5387 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024916.pdf [firstpage_image] =>[orig_patent_app_number] => 10737846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737846
Cell array block of FeRAM, and FeRAM using cell array Dec 17, 2003 Issued
Array ( [id] => 7274303 [patent_doc_number] => 20040233754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor memory device having sense amplifier and method for overdriving the sense amplifier' [patent_app_type] => new [patent_app_number] => 10/737844 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5045 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233754.pdf [firstpage_image] =>[orig_patent_app_number] => 10737844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737844
Semiconductor memory device having sense amplifier and method for overdriving the sense amplifier Dec 17, 2003 Issued
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