Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 997863 [patent_doc_number] => 06914837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'DRAM memory with a shared sense amplifier structure' [patent_app_type] => utility [patent_app_number] => 10/761242 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914837.pdf [firstpage_image] =>[orig_patent_app_number] => 10761242 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761242
DRAM memory with a shared sense amplifier structure Jan 21, 2004 Issued
Array ( [id] => 7059859 [patent_doc_number] => 20050002219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Methods and devices for preventing data stored in memory from being read out' [patent_app_type] => utility [patent_app_number] => 10/761396 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8088 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20050002219.pdf [firstpage_image] =>[orig_patent_app_number] => 10761396 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761396
Methods and devices for preventing data stored in memory from being read out Jan 21, 2004 Issued
Array ( [id] => 944829 [patent_doc_number] => 06967885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Concurrent refresh mode with distributed row address counters in an embedded DRAM' [patent_app_type] => utility [patent_app_number] => 10/757846 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3943 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967885.pdf [firstpage_image] =>[orig_patent_app_number] => 10757846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757846
Concurrent refresh mode with distributed row address counters in an embedded DRAM Jan 14, 2004 Issued
Array ( [id] => 959431 [patent_doc_number] => 06954379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Power-on reset circuit for erasing of split gate flash memory reference cells' [patent_app_type] => utility [patent_app_number] => 10/755496 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2010 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954379.pdf [firstpage_image] =>[orig_patent_app_number] => 10755496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755496
Power-on reset circuit for erasing of split gate flash memory reference cells Jan 11, 2004 Issued
Array ( [id] => 944814 [patent_doc_number] => 06967870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Combination NAND-NOR memory device' [patent_app_type] => utility [patent_app_number] => 10/753644 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967870.pdf [firstpage_image] =>[orig_patent_app_number] => 10753644 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753644
Combination NAND-NOR memory device Jan 6, 2004 Issued
Array ( [id] => 745547 [patent_doc_number] => 07031191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Stabilization method for drain voltage in non-volatile multi-level memory cells and related memory device' [patent_app_type] => utility [patent_app_number] => 10/748701 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2536 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/031/07031191.pdf [firstpage_image] =>[orig_patent_app_number] => 10748701 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748701
Stabilization method for drain voltage in non-volatile multi-level memory cells and related memory device Dec 29, 2003 Issued
Array ( [id] => 689022 [patent_doc_number] => 07079420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Method for operating a memory device' [patent_app_type] => utility [patent_app_number] => 10/747217 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4172 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/079/07079420.pdf [firstpage_image] =>[orig_patent_app_number] => 10747217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747217
Method for operating a memory device Dec 29, 2003 Issued
Array ( [id] => 531741 [patent_doc_number] => 07187605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 10/747400 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5543 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187605.pdf [firstpage_image] =>[orig_patent_app_number] => 10747400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747400
Semiconductor storage device Dec 29, 2003 Issued
Array ( [id] => 741545 [patent_doc_number] => 07035142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Non volatile memory device including a predetermined number of sectors' [patent_app_type] => utility [patent_app_number] => 10/748696 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1697 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035142.pdf [firstpage_image] =>[orig_patent_app_number] => 10748696 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748696
Non volatile memory device including a predetermined number of sectors Dec 29, 2003 Issued
Array ( [id] => 1007162 [patent_doc_number] => 06906973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Bit-line droop reduction' [patent_app_type] => utility [patent_app_number] => 10/746148 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 1953 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906973.pdf [firstpage_image] =>[orig_patent_app_number] => 10746148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746148
Bit-line droop reduction Dec 23, 2003 Issued
Array ( [id] => 7274303 [patent_doc_number] => 20040233754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor memory device having sense amplifier and method for overdriving the sense amplifier' [patent_app_type] => new [patent_app_number] => 10/737844 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5045 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233754.pdf [firstpage_image] =>[orig_patent_app_number] => 10737844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737844
Semiconductor memory device having sense amplifier and method for overdriving the sense amplifier Dec 17, 2003 Issued
Array ( [id] => 7398308 [patent_doc_number] => 20040174745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Drain pump for flash memory' [patent_app_type] => new [patent_app_number] => 10/739244 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2165 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20040174745.pdf [firstpage_image] =>[orig_patent_app_number] => 10739244 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739244
Drain pump for flash memory Dec 17, 2003 Issued
Array ( [id] => 7257201 [patent_doc_number] => 20040240279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Boosting circuit in semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/739249 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4430 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240279.pdf [firstpage_image] =>[orig_patent_app_number] => 10739249 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739249
Boosting circuit in semiconductor memory device Dec 17, 2003 Issued
Array ( [id] => 7150612 [patent_doc_number] => 20050024916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'CELL ARRAY BLOCK OF FERAM, AND FERAM USING CELL ARRAY' [patent_app_type] => utility [patent_app_number] => 10/737846 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5387 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024916.pdf [firstpage_image] =>[orig_patent_app_number] => 10737846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737846
Cell array block of FeRAM, and FeRAM using cell array Dec 17, 2003 Issued
Array ( [id] => 7121346 [patent_doc_number] => 20050013175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING OVER-DRIVING SCHEME' [patent_app_type] => utility [patent_app_number] => 10/737546 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2636 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20050013175.pdf [firstpage_image] =>[orig_patent_app_number] => 10737546 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737546
Semiconductor memory device having over-driving scheme Dec 14, 2003 Issued
Array ( [id] => 7096364 [patent_doc_number] => 20050128822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Voltage translator for multiple voltage operations' [patent_app_type] => utility [patent_app_number] => 10/734944 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7680 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20050128822.pdf [firstpage_image] =>[orig_patent_app_number] => 10734944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734944
Voltage translator for multiple voltage operations Dec 11, 2003 Issued
Array ( [id] => 7375772 [patent_doc_number] => 20040219745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Memory device for reducing skew of data and address' [patent_app_type] => new [patent_app_number] => 10/732144 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4591 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20040219745.pdf [firstpage_image] =>[orig_patent_app_number] => 10732144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732144
Memory device for reducing skew of data and address Dec 8, 2003 Issued
Array ( [id] => 7614410 [patent_doc_number] => 06898120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/728746 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4925 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898120.pdf [firstpage_image] =>[orig_patent_app_number] => 10728746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728746
Nonvolatile semiconductor memory device Dec 7, 2003 Issued
Array ( [id] => 7172386 [patent_doc_number] => 20050122780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same' [patent_app_type] => utility [patent_app_number] => 10/729844 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17889 [patent_no_of_claims] => 88 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122780.pdf [firstpage_image] =>[orig_patent_app_number] => 10729844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729844
NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same Dec 4, 2003 Issued
Array ( [id] => 1038933 [patent_doc_number] => 06873539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/727742 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 8512 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873539.pdf [firstpage_image] =>[orig_patent_app_number] => 10727742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/727742
Semiconductor device Dec 3, 2003 Issued
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