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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7257201 [patent_doc_number] => 20040240279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Boosting circuit in semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/739249 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4430 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240279.pdf [firstpage_image] =>[orig_patent_app_number] => 10739249 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739249
Boosting circuit in semiconductor memory device Dec 17, 2003 Issued
Array ( [id] => 7398308 [patent_doc_number] => 20040174745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Drain pump for flash memory' [patent_app_type] => new [patent_app_number] => 10/739244 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2165 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20040174745.pdf [firstpage_image] =>[orig_patent_app_number] => 10739244 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739244
Drain pump for flash memory Dec 17, 2003 Issued
Array ( [id] => 7121346 [patent_doc_number] => 20050013175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING OVER-DRIVING SCHEME' [patent_app_type] => utility [patent_app_number] => 10/737546 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2636 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20050013175.pdf [firstpage_image] =>[orig_patent_app_number] => 10737546 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737546
Semiconductor memory device having over-driving scheme Dec 14, 2003 Issued
Array ( [id] => 7096364 [patent_doc_number] => 20050128822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Voltage translator for multiple voltage operations' [patent_app_type] => utility [patent_app_number] => 10/734944 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7680 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20050128822.pdf [firstpage_image] =>[orig_patent_app_number] => 10734944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734944
Voltage translator for multiple voltage operations Dec 11, 2003 Issued
Array ( [id] => 7375772 [patent_doc_number] => 20040219745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Memory device for reducing skew of data and address' [patent_app_type] => new [patent_app_number] => 10/732144 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4591 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20040219745.pdf [firstpage_image] =>[orig_patent_app_number] => 10732144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732144
Memory device for reducing skew of data and address Dec 8, 2003 Issued
Array ( [id] => 7614410 [patent_doc_number] => 06898120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/728746 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4925 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898120.pdf [firstpage_image] =>[orig_patent_app_number] => 10728746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728746
Nonvolatile semiconductor memory device Dec 7, 2003 Issued
Array ( [id] => 7172386 [patent_doc_number] => 20050122780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same' [patent_app_type] => utility [patent_app_number] => 10/729844 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17889 [patent_no_of_claims] => 88 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122780.pdf [firstpage_image] =>[orig_patent_app_number] => 10729844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729844
NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same Dec 4, 2003 Issued
Array ( [id] => 1038933 [patent_doc_number] => 06873539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/727742 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 8512 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873539.pdf [firstpage_image] =>[orig_patent_app_number] => 10727742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/727742
Semiconductor device Dec 3, 2003 Issued
Array ( [id] => 1064762 [patent_doc_number] => 06850430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Regulating a magnetic memory cell write current' [patent_app_type] => utility [patent_app_number] => 10/725746 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5235 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/850/06850430.pdf [firstpage_image] =>[orig_patent_app_number] => 10725746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725746
Regulating a magnetic memory cell write current Dec 1, 2003 Issued
Array ( [id] => 657246 [patent_doc_number] => 07110283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Semiconductor memory device and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/722461 [patent_app_country] => US [patent_app_date] => 2003-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10896 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/110/07110283.pdf [firstpage_image] =>[orig_patent_app_number] => 10722461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722461
Semiconductor memory device and semiconductor integrated circuit Nov 27, 2003 Issued
Array ( [id] => 7320541 [patent_doc_number] => 20040136248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/724565 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 25972 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20040136248.pdf [firstpage_image] =>[orig_patent_app_number] => 10724565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724565
Semiconductor memory with self fuse programming Nov 25, 2003 Issued
Array ( [id] => 7287876 [patent_doc_number] => 20040109353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Semiconductor memory device and method for correcting a reference cell' [patent_app_type] => new [patent_app_number] => 10/723143 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5330 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20040109353.pdf [firstpage_image] =>[orig_patent_app_number] => 10723143 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/723143
Semiconductor memory device and method for correcting a reference cell Nov 24, 2003 Issued
Array ( [id] => 1000777 [patent_doc_number] => 06912172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Semiconductor device and method of the semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/718562 [patent_app_country] => US [patent_app_date] => 2003-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 13650 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912172.pdf [firstpage_image] =>[orig_patent_app_number] => 10718562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/718562
Semiconductor device and method of the semiconductor device Nov 23, 2003 Issued
Array ( [id] => 1032624 [patent_doc_number] => 06879518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'Embedded memory with security row lock protection' [patent_app_type] => utility [patent_app_number] => 10/718748 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2742 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/879/06879518.pdf [firstpage_image] =>[orig_patent_app_number] => 10718748 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/718748
Embedded memory with security row lock protection Nov 20, 2003 Issued
Array ( [id] => 697612 [patent_doc_number] => 07072205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Floating-body DRAM with two-phase write' [patent_app_type] => utility [patent_app_number] => 10/716755 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5194 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/072/07072205.pdf [firstpage_image] =>[orig_patent_app_number] => 10716755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716755
Floating-body DRAM with two-phase write Nov 18, 2003 Issued
Array ( [id] => 7102628 [patent_doc_number] => 20050105354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'BITLINE PRECHARGE TIMING SCHEME TO IMPROVE SIGNAL MARGIN' [patent_app_type] => utility [patent_app_number] => 10/717146 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4385 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20050105354.pdf [firstpage_image] =>[orig_patent_app_number] => 10717146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/717146
Bitline precharge timing scheme to improve signal margin Nov 17, 2003 Issued
Array ( [id] => 1054762 [patent_doc_number] => 06859402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Circuit for lines with multiple drivers' [patent_app_type] => utility [patent_app_number] => 10/715311 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5737 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859402.pdf [firstpage_image] =>[orig_patent_app_number] => 10715311 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/715311
Circuit for lines with multiple drivers Nov 16, 2003 Issued
Array ( [id] => 1074620 [patent_doc_number] => 06839288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Latch scheme with invalid command detector' [patent_app_type] => utility [patent_app_number] => 10/706146 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839288.pdf [firstpage_image] =>[orig_patent_app_number] => 10706146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706146
Latch scheme with invalid command detector Nov 11, 2003 Issued
Array ( [id] => 7162964 [patent_doc_number] => 20040076055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Delay lock loop circuit useful in a synchronous system and associated methods' [patent_app_type] => new [patent_app_number] => 10/706003 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 14951 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20040076055.pdf [firstpage_image] =>[orig_patent_app_number] => 10706003 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706003
Delay lock loop circuit useful in a synchronous system and associated methods Nov 11, 2003 Issued
Array ( [id] => 7210989 [patent_doc_number] => 20040071012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Method of retaining memory state in a programmable conductor RAM' [patent_app_type] => new [patent_app_number] => 10/701106 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3444 [patent_no_of_claims] => 98 [patent_no_of_ind_claims] => 35 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20040071012.pdf [firstpage_image] =>[orig_patent_app_number] => 10701106 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/701106
Method of retaining memory state in a programmable conductor RAM Nov 4, 2003 Issued
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