
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1064762
[patent_doc_number] => 06850430
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-01
[patent_title] => 'Regulating a magnetic memory cell write current'
[patent_app_type] => utility
[patent_app_number] => 10/725746
[patent_app_country] => US
[patent_app_date] => 2003-12-02
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[patent_no_of_words] => 5235
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[pdf_file] => patents/06/850/06850430.pdf
[firstpage_image] =>[orig_patent_app_number] => 10725746
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/725746 | Regulating a magnetic memory cell write current | Dec 1, 2003 | Issued |
Array
(
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[patent_doc_number] => 07110283
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Semiconductor memory device and semiconductor integrated circuit'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/722461 | Semiconductor memory device and semiconductor integrated circuit | Nov 27, 2003 | Issued |
Array
(
[id] => 7320541
[patent_doc_number] => 20040136248
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[patent_kind] => A1
[patent_issue_date] => 2004-07-15
[patent_title] => 'Semiconductor memory'
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[patent_app_number] => 10/724565
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[patent_app_date] => 2003-11-26
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[patent_drawing_sheets_cnt] => 36
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/724565 | Semiconductor memory with self fuse programming | Nov 25, 2003 | Issued |
Array
(
[id] => 7287876
[patent_doc_number] => 20040109353
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[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Semiconductor memory device and method for correcting a reference cell'
[patent_app_type] => new
[patent_app_number] => 10/723143
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/723143 | Semiconductor memory device and method for correcting a reference cell | Nov 24, 2003 | Issued |
Array
(
[id] => 1000777
[patent_doc_number] => 06912172
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[patent_issue_date] => 2005-06-28
[patent_title] => 'Semiconductor device and method of the semiconductor device'
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[firstpage_image] =>[orig_patent_app_number] => 10718562
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/718562 | Semiconductor device and method of the semiconductor device | Nov 23, 2003 | Issued |
Array
(
[id] => 1032624
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[patent_title] => 'Embedded memory with security row lock protection'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/718748 | Embedded memory with security row lock protection | Nov 20, 2003 | Issued |
Array
(
[id] => 697612
[patent_doc_number] => 07072205
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[patent_issue_date] => 2006-07-04
[patent_title] => 'Floating-body DRAM with two-phase write'
[patent_app_type] => utility
[patent_app_number] => 10/716755
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[pdf_file] => patents/07/072/07072205.pdf
[firstpage_image] =>[orig_patent_app_number] => 10716755
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/716755 | Floating-body DRAM with two-phase write | Nov 18, 2003 | Issued |
Array
(
[id] => 7102628
[patent_doc_number] => 20050105354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'BITLINE PRECHARGE TIMING SCHEME TO IMPROVE SIGNAL MARGIN'
[patent_app_type] => utility
[patent_app_number] => 10/717146
[patent_app_country] => US
[patent_app_date] => 2003-11-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/717146 | Bitline precharge timing scheme to improve signal margin | Nov 17, 2003 | Issued |
Array
(
[id] => 1054762
[patent_doc_number] => 06859402
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-22
[patent_title] => 'Circuit for lines with multiple drivers'
[patent_app_type] => utility
[patent_app_number] => 10/715311
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[firstpage_image] =>[orig_patent_app_number] => 10715311
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/715311 | Circuit for lines with multiple drivers | Nov 16, 2003 | Issued |
Array
(
[id] => 1074620
[patent_doc_number] => 06839288
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-01-04
[patent_title] => 'Latch scheme with invalid command detector'
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[firstpage_image] =>[orig_patent_app_number] => 10706146
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Array
(
[id] => 7162964
[patent_doc_number] => 20040076055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'Delay lock loop circuit useful in a synchronous system and associated methods'
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[firstpage_image] =>[orig_patent_app_number] => 10706003
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/706003 | Delay lock loop circuit useful in a synchronous system and associated methods | Nov 11, 2003 | Issued |
Array
(
[id] => 7210989
[patent_doc_number] => 20040071012
[patent_country] => US
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[patent_title] => 'Method of retaining memory state in a programmable conductor RAM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/701106 | Method of retaining memory state in a programmable conductor RAM | Nov 4, 2003 | Issued |
Array
(
[id] => 784551
[patent_doc_number] => 06992932
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[patent_title] => 'Method circuit and system for read error detection in a non-volatile memory array'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/695457 | Method circuit and system for read error detection in a non-volatile memory array | Oct 28, 2003 | Issued |
Array
(
[id] => 7320503
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[patent_title] => 'Method circuit and system for determining a reference voltage'
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[firstpage_image] =>[orig_patent_app_number] => 10695448
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/695448 | Method circuit and system for determining a reference voltage | Oct 28, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/696144 | Semiconductor memory device with reduced data access time | Oct 27, 2003 | Issued |
Array
(
[id] => 784578
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[patent_title] => 'Fuse circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/692951 | Fuse circuit | Oct 26, 2003 | Issued |
Array
(
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Array
(
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/689144 | Magnetic memory which detects changes between first and second resistive states of memory cell | Oct 19, 2003 | Issued |