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Array ( [id] => 784551 [patent_doc_number] => 06992932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Method circuit and system for read error detection in a non-volatile memory array' [patent_app_type] => utility [patent_app_number] => 10/695457 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7332 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992932.pdf [firstpage_image] =>[orig_patent_app_number] => 10695457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7320503 [patent_doc_number] => 20040136220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Method circuit and system for determining a reference voltage' [patent_app_type] => new [patent_app_number] => 10/695448 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4889 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20040136220.pdf [firstpage_image] =>[orig_patent_app_number] => 10695448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 973991 [patent_doc_number] => 06937535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Semiconductor memory device with reduced data access time' [patent_app_type] => utility [patent_app_number] => 10/696144 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 22530 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/937/06937535.pdf [firstpage_image] =>[orig_patent_app_number] => 10696144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 784578 [patent_doc_number] => 06992945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Fuse circuit' [patent_app_type] => utility [patent_app_number] => 10/692951 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 15712 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992945.pdf [firstpage_image] =>[orig_patent_app_number] => 10692951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7274289 [patent_doc_number] => 20040233740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/690698 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7405 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233740.pdf [firstpage_image] =>[orig_patent_app_number] => 10690698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7156944 [patent_doc_number] => 20050083748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Magnetic memory having a calibration system' [patent_app_type] => utility [patent_app_number] => 10/690249 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7927 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083748.pdf [firstpage_image] =>[orig_patent_app_number] => 10690249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7342586 [patent_doc_number] => 20040246805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Semiconductor memory device capable of controlling potential level of power supply line and/or ground line' [patent_app_type] => new [patent_app_number] => 10/689344 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22821 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246805.pdf [firstpage_image] =>[orig_patent_app_number] => 10689344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1067359 [patent_doc_number] => 06847544 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-25 [patent_title] => 'Magnetic memory which detects changes between first and second resistive states of memory cell' [patent_app_type] => utility [patent_app_number] => 10/689144 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6812 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/847/06847544.pdf [firstpage_image] =>[orig_patent_app_number] => 10689144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1084386 [patent_doc_number] => 06834007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/681247 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3863 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834007.pdf [firstpage_image] =>[orig_patent_app_number] => 10681247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7247250 [patent_doc_number] => 20050073871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Nondestructive read, two-switch, single-charge-storage device RAM devices' [patent_app_type] => utility [patent_app_number] => 10/680348 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7420 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073871.pdf [firstpage_image] =>[orig_patent_app_number] => 10680348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 980381 [patent_doc_number] => 06930912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Magnetic memory and driving method therefor' [patent_app_type] => utility [patent_app_number] => 10/677311 [patent_app_country] => US [patent_app_date] => 2003-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6982 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930912.pdf [firstpage_image] =>[orig_patent_app_number] => 10677311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7297860 [patent_doc_number] => 20040125682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/677686 [patent_app_country] => US [patent_app_date] => 2003-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13615 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20040125682.pdf [firstpage_image] =>[orig_patent_app_number] => 10677686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7614406 [patent_doc_number] => 06898124 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Efficient and accurate sensing circuit and technique for low voltage flash memory devices' [patent_app_type] => utility [patent_app_number] => 10/678446 [patent_app_country] => US [patent_app_date] => 2003-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898124.pdf [firstpage_image] =>[orig_patent_app_number] => 10678446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7279726 [patent_doc_number] => 20040062103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Memory circuit with a test mode for writing test data' [patent_app_type] => new [patent_app_number] => 10/676597 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3128 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20040062103.pdf [firstpage_image] =>[orig_patent_app_number] => 10676597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1051704 [patent_doc_number] => 06862238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'Memory system with reduced refresh current' [patent_app_type] => utility [patent_app_number] => 10/672244 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862238.pdf [firstpage_image] =>[orig_patent_app_number] => 10672244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5594120 [patent_doc_number] => 20060158036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Backup circuit' [patent_app_type] => utility [patent_app_number] => 10/563580 [patent_app_country] => US [patent_app_date] => 2003-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3943 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20060158036.pdf [firstpage_image] =>[orig_patent_app_number] => 10563580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 980444 [patent_doc_number] => 06930939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Semiconductor memory device having hierarchical structure of data input/output line and precharge method thereof' [patent_app_type] => utility [patent_app_number] => 10/660568 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4195 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930939.pdf [firstpage_image] =>[orig_patent_app_number] => 10660568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 899292 [patent_doc_number] => RE040110 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2008-02-26 [patent_title] => 'Nonvolatile semiconductor memory device for storing multivalued data' [patent_app_type] => reissue [patent_app_number] => 10/658850 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 13325 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040110.pdf [firstpage_image] =>[orig_patent_app_number] => 10658850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1130932 [patent_doc_number] => 06791873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Apparatus and method for generating a write current for a magnetic memory cell' [patent_app_type] => B1 [patent_app_number] => 10/658442 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4677 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791873.pdf [firstpage_image] =>[orig_patent_app_number] => 10658442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1054738 [patent_doc_number] => 06859388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Circuit for write field disturbance cancellation in an MRAM and method of operation' [patent_app_type] => utility [patent_app_number] => 10/656646 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5703 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859388.pdf [firstpage_image] =>[orig_patent_app_number] => 10656646 [rel_patent_id] =>[rel_patent_doc_number] =>)