
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1084386
[patent_doc_number] => 06834007
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-21
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 10/681247
[patent_app_country] => US
[patent_app_date] => 2003-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3863
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/834/06834007.pdf
[firstpage_image] =>[orig_patent_app_number] => 10681247
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/681247 | Semiconductor memory device | Oct 8, 2003 | Issued |
Array
(
[id] => 7247250
[patent_doc_number] => 20050073871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Nondestructive read, two-switch, single-charge-storage device RAM devices'
[patent_app_type] => utility
[patent_app_number] => 10/680348
[patent_app_country] => US
[patent_app_date] => 2003-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7420
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20050073871.pdf
[firstpage_image] =>[orig_patent_app_number] => 10680348
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680348 | Nondestructive read, two-switch, single-charge-storage device RAM devices | Oct 6, 2003 | Issued |
Array
(
[id] => 7297860
[patent_doc_number] => 20040125682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/677686
[patent_app_country] => US
[patent_app_date] => 2003-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 13615
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20040125682.pdf
[firstpage_image] =>[orig_patent_app_number] => 10677686
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677686 | Semiconductor device | Oct 2, 2003 | Issued |
Array
(
[id] => 7614406
[patent_doc_number] => 06898124
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-05-24
[patent_title] => 'Efficient and accurate sensing circuit and technique for low voltage flash memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/678446
[patent_app_country] => US
[patent_app_date] => 2003-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3311
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/898/06898124.pdf
[firstpage_image] =>[orig_patent_app_number] => 10678446
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/678446 | Efficient and accurate sensing circuit and technique for low voltage flash memory devices | Oct 2, 2003 | Issued |
Array
(
[id] => 980381
[patent_doc_number] => 06930912
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Magnetic memory and driving method therefor'
[patent_app_type] => utility
[patent_app_number] => 10/677311
[patent_app_country] => US
[patent_app_date] => 2003-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 6982
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/930/06930912.pdf
[firstpage_image] =>[orig_patent_app_number] => 10677311
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677311 | Magnetic memory and driving method therefor | Oct 2, 2003 | Issued |
Array
(
[id] => 7279726
[patent_doc_number] => 20040062103
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Memory circuit with a test mode for writing test data'
[patent_app_type] => new
[patent_app_number] => 10/676597
[patent_app_country] => US
[patent_app_date] => 2003-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3128
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0062/20040062103.pdf
[firstpage_image] =>[orig_patent_app_number] => 10676597
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/676597 | Memory circuit with a test mode for writing test data | Sep 30, 2003 | Abandoned |
Array
(
[id] => 1051704
[patent_doc_number] => 06862238
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-01
[patent_title] => 'Memory system with reduced refresh current'
[patent_app_type] => utility
[patent_app_number] => 10/672244
[patent_app_country] => US
[patent_app_date] => 2003-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3866
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/862/06862238.pdf
[firstpage_image] =>[orig_patent_app_number] => 10672244
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/672244 | Memory system with reduced refresh current | Sep 24, 2003 | Issued |
Array
(
[id] => 5594120
[patent_doc_number] => 20060158036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Backup circuit'
[patent_app_type] => utility
[patent_app_number] => 10/563580
[patent_app_country] => US
[patent_app_date] => 2003-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3943
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20060158036.pdf
[firstpage_image] =>[orig_patent_app_number] => 10563580
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/563580 | Backup circuit for holding information in a storage circuit when power cut-off occurs | Sep 17, 2003 | Issued |
Array
(
[id] => 980444
[patent_doc_number] => 06930939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Semiconductor memory device having hierarchical structure of data input/output line and precharge method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/660568
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4195
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/930/06930939.pdf
[firstpage_image] =>[orig_patent_app_number] => 10660568
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/660568 | Semiconductor memory device having hierarchical structure of data input/output line and precharge method thereof | Sep 11, 2003 | Issued |
Array
(
[id] => 899292
[patent_doc_number] => RE040110
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2008-02-26
[patent_title] => 'Nonvolatile semiconductor memory device for storing multivalued data'
[patent_app_type] => reissue
[patent_app_number] => 10/658850
[patent_app_country] => US
[patent_app_date] => 2003-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 31
[patent_no_of_words] => 13325
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/040/RE040110.pdf
[firstpage_image] =>[orig_patent_app_number] => 10658850
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/658850 | Nonvolatile semiconductor memory device for storing multivalued data | Sep 9, 2003 | Issued |
Array
(
[id] => 1130932
[patent_doc_number] => 06791873
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-14
[patent_title] => 'Apparatus and method for generating a write current for a magnetic memory cell'
[patent_app_type] => B1
[patent_app_number] => 10/658442
[patent_app_country] => US
[patent_app_date] => 2003-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4677
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/791/06791873.pdf
[firstpage_image] =>[orig_patent_app_number] => 10658442
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/658442 | Apparatus and method for generating a write current for a magnetic memory cell | Sep 7, 2003 | Issued |
Array
(
[id] => 1054738
[patent_doc_number] => 06859388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-22
[patent_title] => 'Circuit for write field disturbance cancellation in an MRAM and method of operation'
[patent_app_type] => utility
[patent_app_number] => 10/656646
[patent_app_country] => US
[patent_app_date] => 2003-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5703
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/859/06859388.pdf
[firstpage_image] =>[orig_patent_app_number] => 10656646
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/656646 | Circuit for write field disturbance cancellation in an MRAM and method of operation | Sep 4, 2003 | Issued |
Array
(
[id] => 1118218
[patent_doc_number] => 06801460
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-05
[patent_title] => 'Semiconductor memory device suppressing peak current'
[patent_app_type] => B2
[patent_app_number] => 10/654948
[patent_app_country] => US
[patent_app_date] => 2003-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 21
[patent_no_of_words] => 10301
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/801/06801460.pdf
[firstpage_image] =>[orig_patent_app_number] => 10654948
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/654948 | Semiconductor memory device suppressing peak current | Sep 4, 2003 | Issued |
Array
(
[id] => 997855
[patent_doc_number] => 06914832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-05
[patent_title] => 'Semiconductor memory device with memory cell array divided into blocks'
[patent_app_type] => utility
[patent_app_number] => 10/652563
[patent_app_country] => US
[patent_app_date] => 2003-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4091
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/914/06914832.pdf
[firstpage_image] =>[orig_patent_app_number] => 10652563
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/652563 | Semiconductor memory device with memory cell array divided into blocks | Sep 1, 2003 | Issued |
Array
(
[id] => 710572
[patent_doc_number] => 07061820
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Voltage keeping scheme for low-leakage memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/649266
[patent_app_country] => US
[patent_app_date] => 2003-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6470
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/061/07061820.pdf
[firstpage_image] =>[orig_patent_app_number] => 10649266
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/649266 | Voltage keeping scheme for low-leakage memory devices | Aug 26, 2003 | Issued |
Array
(
[id] => 771990
[patent_doc_number] => 07006369
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-28
[patent_title] => 'Design and use of a spacer cell to support reconfigurable memories'
[patent_app_type] => utility
[patent_app_number] => 10/650192
[patent_app_country] => US
[patent_app_date] => 2003-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 4133
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/006/07006369.pdf
[firstpage_image] =>[orig_patent_app_number] => 10650192
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/650192 | Design and use of a spacer cell to support reconfigurable memories | Aug 26, 2003 | Issued |
Array
(
[id] => 973938
[patent_doc_number] => 06937514
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-30
[patent_title] => 'Semiconductor memory device including MOS transistors each having a floating gate and a control gate'
[patent_app_type] => utility
[patent_app_number] => 10/647242
[patent_app_country] => US
[patent_app_date] => 2003-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 11974
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/937/06937514.pdf
[firstpage_image] =>[orig_patent_app_number] => 10647242
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/647242 | Semiconductor memory device including MOS transistors each having a floating gate and a control gate | Aug 25, 2003 | Issued |
Array
(
[id] => 1023655
[patent_doc_number] => 06888759
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch'
[patent_app_type] => utility
[patent_app_number] => 10/644744
[patent_app_country] => US
[patent_app_date] => 2003-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 8480
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/888/06888759.pdf
[firstpage_image] =>[orig_patent_app_number] => 10644744
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/644744 | Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch | Aug 20, 2003 | Issued |
Array
(
[id] => 1095646
[patent_doc_number] => 06826115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-30
[patent_title] => 'Circuits and methods for providing page mode operation in semiconductor memory device having partial activation architecture'
[patent_app_type] => B2
[patent_app_number] => 10/640146
[patent_app_country] => US
[patent_app_date] => 2003-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 11309
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/826/06826115.pdf
[firstpage_image] =>[orig_patent_app_number] => 10640146
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/640146 | Circuits and methods for providing page mode operation in semiconductor memory device having partial activation architecture | Aug 12, 2003 | Issued |
Array
(
[id] => 1118197
[patent_doc_number] => 06801455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-05
[patent_title] => 'Voltage generation circuit for non-volatile semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 10/639643
[patent_app_country] => US
[patent_app_date] => 2003-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 9321
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/801/06801455.pdf
[firstpage_image] =>[orig_patent_app_number] => 10639643
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639643 | Voltage generation circuit for non-volatile semiconductor memory device | Aug 12, 2003 | Issued |