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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1118218 [patent_doc_number] => 06801460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Semiconductor memory device suppressing peak current' [patent_app_type] => B2 [patent_app_number] => 10/654948 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 10301 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801460.pdf [firstpage_image] =>[orig_patent_app_number] => 10654948 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654948
Semiconductor memory device suppressing peak current Sep 4, 2003 Issued
Array ( [id] => 997855 [patent_doc_number] => 06914832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Semiconductor memory device with memory cell array divided into blocks' [patent_app_type] => utility [patent_app_number] => 10/652563 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4091 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914832.pdf [firstpage_image] =>[orig_patent_app_number] => 10652563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/652563
Semiconductor memory device with memory cell array divided into blocks Sep 1, 2003 Issued
Array ( [id] => 710572 [patent_doc_number] => 07061820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Voltage keeping scheme for low-leakage memory devices' [patent_app_type] => utility [patent_app_number] => 10/649266 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6470 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061820.pdf [firstpage_image] =>[orig_patent_app_number] => 10649266 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649266
Voltage keeping scheme for low-leakage memory devices Aug 26, 2003 Issued
Array ( [id] => 771990 [patent_doc_number] => 07006369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Design and use of a spacer cell to support reconfigurable memories' [patent_app_type] => utility [patent_app_number] => 10/650192 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4133 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/006/07006369.pdf [firstpage_image] =>[orig_patent_app_number] => 10650192 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/650192
Design and use of a spacer cell to support reconfigurable memories Aug 26, 2003 Issued
Array ( [id] => 973938 [patent_doc_number] => 06937514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Semiconductor memory device including MOS transistors each having a floating gate and a control gate' [patent_app_type] => utility [patent_app_number] => 10/647242 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 11974 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/937/06937514.pdf [firstpage_image] =>[orig_patent_app_number] => 10647242 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/647242
Semiconductor memory device including MOS transistors each having a floating gate and a control gate Aug 25, 2003 Issued
Array ( [id] => 1023655 [patent_doc_number] => 06888759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch' [patent_app_type] => utility [patent_app_number] => 10/644744 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8480 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888759.pdf [firstpage_image] =>[orig_patent_app_number] => 10644744 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/644744
Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch Aug 20, 2003 Issued
Array ( [id] => 1118197 [patent_doc_number] => 06801455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Voltage generation circuit for non-volatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/639643 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9321 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801455.pdf [firstpage_image] =>[orig_patent_app_number] => 10639643 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/639643
Voltage generation circuit for non-volatile semiconductor memory device Aug 12, 2003 Issued
Array ( [id] => 1095646 [patent_doc_number] => 06826115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Circuits and methods for providing page mode operation in semiconductor memory device having partial activation architecture' [patent_app_type] => B2 [patent_app_number] => 10/640146 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11309 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826115.pdf [firstpage_image] =>[orig_patent_app_number] => 10640146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640146
Circuits and methods for providing page mode operation in semiconductor memory device having partial activation architecture Aug 12, 2003 Issued
Array ( [id] => 7131932 [patent_doc_number] => 20040042325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Static semiconductor memory device and method of controlling the same' [patent_app_type] => new [patent_app_number] => 10/636543 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4292 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042325.pdf [firstpage_image] =>[orig_patent_app_number] => 10636543 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/636543
Static semiconductor memory device and method of controlling the same Aug 7, 2003 Issued
Array ( [id] => 1036120 [patent_doc_number] => 06876568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Timing adjusting circuit and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/636544 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/876/06876568.pdf [firstpage_image] =>[orig_patent_app_number] => 10636544 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/636544
Timing adjusting circuit and semiconductor memory device Aug 7, 2003 Issued
Array ( [id] => 7374837 [patent_doc_number] => 20040027897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Bit line pre-charge circuit of semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/633562 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7909 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027897.pdf [firstpage_image] =>[orig_patent_app_number] => 10633562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633562
Bit line pre-charge circuit of semiconductor memory device Aug 4, 2003 Issued
Array ( [id] => 7131930 [patent_doc_number] => 20040042324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Flash memory for reducing peak current' [patent_app_type] => new [patent_app_number] => 10/633848 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3949 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042324.pdf [firstpage_image] =>[orig_patent_app_number] => 10633848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633848
Flash memory for reducing peak current Aug 3, 2003 Issued
Array ( [id] => 736694 [patent_doc_number] => 07038935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => '2-terminal trapped charge memory device with voltage switchable multi-level resistance' [patent_app_type] => utility [patent_app_number] => 10/634636 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6262 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038935.pdf [firstpage_image] =>[orig_patent_app_number] => 10634636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634636
2-terminal trapped charge memory device with voltage switchable multi-level resistance Aug 3, 2003 Issued
Array ( [id] => 1091249 [patent_doc_number] => 06829182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => B2 [patent_app_number] => 10/633956 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3193 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829182.pdf [firstpage_image] =>[orig_patent_app_number] => 10633956 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633956
Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines Aug 3, 2003 Issued
Array ( [id] => 7374652 [patent_doc_number] => 20040027863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Semiconductor memory device with shift redundancy circuits' [patent_app_type] => new [patent_app_number] => 10/631766 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8199 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027863.pdf [firstpage_image] =>[orig_patent_app_number] => 10631766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631766
Semiconductor memory device with shift redundancy circuits Jul 31, 2003 Issued
Array ( [id] => 1104554 [patent_doc_number] => 06816414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'Nonvolatile memory and method of making same' [patent_app_type] => B1 [patent_app_number] => 10/631142 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3178 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816414.pdf [firstpage_image] =>[orig_patent_app_number] => 10631142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631142
Nonvolatile memory and method of making same Jul 30, 2003 Issued
Array ( [id] => 7346717 [patent_doc_number] => 20040047207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Reading circuit, reference circuit, and semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/630568 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 22542 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20040047207.pdf [firstpage_image] =>[orig_patent_app_number] => 10630568 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630568
Reading circuit, reference circuit, and semiconductor memory device Jul 28, 2003 Issued
Array ( [id] => 714029 [patent_doc_number] => 07057960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-06 [patent_title] => 'Method and architecture for reducing the power consumption for memory devices in refresh operations' [patent_app_type] => utility [patent_app_number] => 10/629667 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4655 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057960.pdf [firstpage_image] =>[orig_patent_app_number] => 10629667 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629667
Method and architecture for reducing the power consumption for memory devices in refresh operations Jul 28, 2003 Issued
Array ( [id] => 7150681 [patent_doc_number] => 20050024939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Detecting over programmed memory' [patent_app_type] => utility [patent_app_number] => 10/629068 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14097 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024939.pdf [firstpage_image] =>[orig_patent_app_number] => 10629068 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629068
Detecting over programmed memory Jul 28, 2003 Issued
Array ( [id] => 7614417 [patent_doc_number] => 06898113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Magnetic memory device with reference cell for data reading' [patent_app_type] => utility [patent_app_number] => 10/628463 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 15133 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898113.pdf [firstpage_image] =>[orig_patent_app_number] => 10628463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/628463
Magnetic memory device with reference cell for data reading Jul 28, 2003 Issued
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