
Son Luu Mai
Examiner (ID: 18155)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818 |
| Total Applications | 3063 |
| Issued Applications | 2917 |
| Pending Applications | 45 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1204590
[patent_doc_number] => 06721199
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-13
[patent_title] => 'Nonvolatile ferroelectric memory device and method for operating main bitline load controller thereof'
[patent_app_type] => B2
[patent_app_number] => 10/307950
[patent_app_country] => US
[patent_app_date] => 2002-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 24
[patent_no_of_words] => 8172
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/721/06721199.pdf
[firstpage_image] =>[orig_patent_app_number] => 10307950
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/307950 | Nonvolatile ferroelectric memory device and method for operating main bitline load controller thereof | Dec 2, 2002 | Issued |
Array
(
[id] => 6790951
[patent_doc_number] => 20030086295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-08
[patent_title] => 'Semiconductor device that enables simultaneous read and write/read operation'
[patent_app_type] => new
[patent_app_number] => 10/307283
[patent_app_country] => US
[patent_app_date] => 2002-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 48
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[patent_no_of_words] => 20870
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20030086295.pdf
[firstpage_image] =>[orig_patent_app_number] => 10307283
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/307283 | Semiconductor device that enables simultaneous read and write/read operation | Dec 1, 2002 | Issued |
Array
(
[id] => 6768901
[patent_doc_number] => 20030214841
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2003-11-20
[patent_title] => 'Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device'
[patent_app_type] => corrected
[patent_app_number] => 10/306887
[patent_app_country] => US
[patent_app_date] => 2002-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 13580
[patent_no_of_claims] => 46
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A9/0214/20030214841.pdf
[firstpage_image] =>[orig_patent_app_number] => 10306887
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/306887 | Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device | Nov 26, 2002 | Issued |
Array
(
[id] => 6768901
[patent_doc_number] => 20030214841
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2003-11-20
[patent_title] => 'Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device'
[patent_app_type] => corrected
[patent_app_number] => 10/306887
[patent_app_country] => US
[patent_app_date] => 2002-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 13580
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 96
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A9/0214/20030214841.pdf
[firstpage_image] =>[orig_patent_app_number] => 10306887
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/306887 | Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device | Nov 26, 2002 | Issued |
Array
(
[id] => 1194926
[patent_doc_number] => 06731554
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-04
[patent_title] => '2T2C signal margin test mode using resistive element'
[patent_app_type] => B1
[patent_app_number] => 10/301546
[patent_app_country] => US
[patent_app_date] => 2002-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3163
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/731/06731554.pdf
[firstpage_image] =>[orig_patent_app_number] => 10301546
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/301546 | 2T2C signal margin test mode using resistive element | Nov 19, 2002 | Issued |
Array
(
[id] => 1155989
[patent_doc_number] => 06775177
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-10
[patent_title] => 'Semiconductor memory device switchable to twin memory cell configuration'
[patent_app_type] => B2
[patent_app_number] => 10/298648
[patent_app_country] => US
[patent_app_date] => 2002-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/775/06775177.pdf
[firstpage_image] =>[orig_patent_app_number] => 10298648
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/298648 | Semiconductor memory device switchable to twin memory cell configuration | Nov 18, 2002 | Issued |
| 10/275952 | Semiconductor memory device | Nov 14, 2002 | Abandoned |
Array
(
[id] => 6759857
[patent_doc_number] => 20030123218
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-03
[patent_title] => 'Arrangement for voltage supply to a volatile semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 10/169446
[patent_app_country] => US
[patent_app_date] => 2002-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2558
[patent_no_of_claims] => 11
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[pdf_file] => publications/A1/0123/20030123218.pdf
[firstpage_image] =>[orig_patent_app_number] => 10169446
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/169446 | Arrangement for voltage supply to a volatile semiconductor memory | Nov 11, 2002 | Issued |
Array
(
[id] => 6667669
[patent_doc_number] => 20030112652
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-19
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/289254
[patent_app_country] => US
[patent_app_date] => 2002-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9370
[patent_no_of_claims] => 12
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[pdf_file] => publications/A1/0112/20030112652.pdf
[firstpage_image] =>[orig_patent_app_number] => 10289254
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/289254 | Semiconductor integrated circuit | Nov 6, 2002 | Abandoned |
Array
(
[id] => 6809323
[patent_doc_number] => 20030199262
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-23
[patent_title] => 'Multi-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereof'
[patent_app_type] => new
[patent_app_number] => 10/288540
[patent_app_country] => US
[patent_app_date] => 2002-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 7804
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[pdf_file] => publications/A1/0199/20030199262.pdf
[firstpage_image] =>[orig_patent_app_number] => 10288540
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/288540 | Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof | Nov 5, 2002 | Issued |
Array
(
[id] => 1174252
[patent_doc_number] => 06757213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-29
[patent_title] => 'Synchronous DRAM controller'
[patent_app_type] => B2
[patent_app_number] => 10/285550
[patent_app_country] => US
[patent_app_date] => 2002-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/757/06757213.pdf
[firstpage_image] =>[orig_patent_app_number] => 10285550
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/285550 | Synchronous DRAM controller | Oct 31, 2002 | Issued |
Array
(
[id] => 1176077
[patent_doc_number] => 06754109
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-22
[patent_title] => 'Method of programming memory cells'
[patent_app_type] => B1
[patent_app_number] => 10/282847
[patent_app_country] => US
[patent_app_date] => 2002-10-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/754/06754109.pdf
[firstpage_image] =>[orig_patent_app_number] => 10282847
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/282847 | Method of programming memory cells | Oct 28, 2002 | Issued |
Array
(
[id] => 7624498
[patent_doc_number] => 06724678
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-20
[patent_title] => 'Nonvolatile semiconductor memory unit'
[patent_app_type] => B2
[patent_app_number] => 10/281249
[patent_app_country] => US
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[pdf_file] => patents/06/724/06724678.pdf
[firstpage_image] =>[orig_patent_app_number] => 10281249
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/281249 | Nonvolatile semiconductor memory unit | Oct 27, 2002 | Issued |
Array
(
[id] => 6790941
[patent_doc_number] => 20030086285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-08
[patent_title] => 'Ferroelectric semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 10/279853
[patent_app_country] => US
[patent_app_date] => 2002-10-25
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20030086285.pdf
[firstpage_image] =>[orig_patent_app_number] => 10279853
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279853 | Ferroelectric semiconductor memory | Oct 24, 2002 | Issued |
Array
(
[id] => 6833629
[patent_doc_number] => 20030161174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 10/277150
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0161/20030161174.pdf
[firstpage_image] =>[orig_patent_app_number] => 10277150
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/277150 | Semiconductor integrated circuit having connecting wires for interconnecting bit lines | Oct 21, 2002 | Issued |
Array
(
[id] => 1191091
[patent_doc_number] => 06735105
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-11
[patent_title] => 'Semiconductor circuit supplied with a varying power supply voltage, and method for operating the same'
[patent_app_type] => B2
[patent_app_number] => 10/277050
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[pdf_file] => patents/06/735/06735105.pdf
[firstpage_image] =>[orig_patent_app_number] => 10277050
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/277050 | Semiconductor circuit supplied with a varying power supply voltage, and method for operating the same | Oct 21, 2002 | Issued |
Array
(
[id] => 7162913
[patent_doc_number] => 20040076042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'High performance memory column group repair scheme with small area penalty'
[patent_app_type] => new
[patent_app_number] => 10/272551
[patent_app_country] => US
[patent_app_date] => 2002-10-16
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[pdf_file] => publications/A1/0076/20040076042.pdf
[firstpage_image] =>[orig_patent_app_number] => 10272551
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/272551 | High performance memory column group repair scheme with small area penalty | Oct 15, 2002 | Abandoned |
Array
(
[id] => 6808158
[patent_doc_number] => 20030198097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-23
[patent_title] => 'Semiconductor memory device having preamplifier with improved data propagation speed'
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[patent_app_number] => 10/270653
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[firstpage_image] =>[orig_patent_app_number] => 10270653
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/270653 | Semiconductor memory device having preamplifier with improved data propagation speed | Oct 15, 2002 | Issued |
Array
(
[id] => 1174127
[patent_doc_number] => 06757200
[patent_country] => US
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[patent_issue_date] => 2004-06-29
[patent_title] => 'Semiconductor memory having dual port cell supporting hidden refresh'
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[firstpage_image] =>[orig_patent_app_number] => 10269599
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/269599 | Semiconductor memory having dual port cell supporting hidden refresh | Oct 9, 2002 | Issued |
Array
(
[id] => 1234523
[patent_doc_number] => 06693838
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[patent_title] => 'Semiconductor memory device equipped with refresh timing signal generator'
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[firstpage_image] =>[orig_patent_app_number] => 10267753
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/267753 | Semiconductor memory device equipped with refresh timing signal generator | Oct 9, 2002 | Issued |