Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6667669 [patent_doc_number] => 20030112652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/289254 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9370 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112652.pdf [firstpage_image] =>[orig_patent_app_number] => 10289254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/289254
Semiconductor integrated circuit Nov 6, 2002 Abandoned
Array ( [id] => 6809323 [patent_doc_number] => 20030199262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Multi-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereof' [patent_app_type] => new [patent_app_number] => 10/288540 [patent_app_country] => US [patent_app_date] => 2002-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20030199262.pdf [firstpage_image] =>[orig_patent_app_number] => 10288540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/288540
Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof Nov 5, 2002 Issued
Array ( [id] => 1174252 [patent_doc_number] => 06757213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Synchronous DRAM controller' [patent_app_type] => B2 [patent_app_number] => 10/285550 [patent_app_country] => US [patent_app_date] => 2002-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 0 [patent_no_of_words] => 3454 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757213.pdf [firstpage_image] =>[orig_patent_app_number] => 10285550 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/285550
Synchronous DRAM controller Oct 31, 2002 Issued
Array ( [id] => 1176077 [patent_doc_number] => 06754109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method of programming memory cells' [patent_app_type] => B1 [patent_app_number] => 10/282847 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2829 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754109.pdf [firstpage_image] =>[orig_patent_app_number] => 10282847 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282847
Method of programming memory cells Oct 28, 2002 Issued
Array ( [id] => 7624498 [patent_doc_number] => 06724678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Nonvolatile semiconductor memory unit' [patent_app_type] => B2 [patent_app_number] => 10/281249 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3224 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724678.pdf [firstpage_image] =>[orig_patent_app_number] => 10281249 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/281249
Nonvolatile semiconductor memory unit Oct 27, 2002 Issued
Array ( [id] => 6790941 [patent_doc_number] => 20030086285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Ferroelectric semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/279853 [patent_app_country] => US [patent_app_date] => 2002-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20030086285.pdf [firstpage_image] =>[orig_patent_app_number] => 10279853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279853
Ferroelectric semiconductor memory Oct 24, 2002 Issued
Array ( [id] => 6833629 [patent_doc_number] => 20030161174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/277150 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7173 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20030161174.pdf [firstpage_image] =>[orig_patent_app_number] => 10277150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/277150
Semiconductor integrated circuit having connecting wires for interconnecting bit lines Oct 21, 2002 Issued
Array ( [id] => 1191091 [patent_doc_number] => 06735105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Semiconductor circuit supplied with a varying power supply voltage, and method for operating the same' [patent_app_type] => B2 [patent_app_number] => 10/277050 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8503 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735105.pdf [firstpage_image] =>[orig_patent_app_number] => 10277050 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/277050
Semiconductor circuit supplied with a varying power supply voltage, and method for operating the same Oct 21, 2002 Issued
Array ( [id] => 7162913 [patent_doc_number] => 20040076042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'High performance memory column group repair scheme with small area penalty' [patent_app_type] => new [patent_app_number] => 10/272551 [patent_app_country] => US [patent_app_date] => 2002-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3396 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20040076042.pdf [firstpage_image] =>[orig_patent_app_number] => 10272551 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/272551
High performance memory column group repair scheme with small area penalty Oct 15, 2002 Abandoned
Array ( [id] => 6808158 [patent_doc_number] => 20030198097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Semiconductor memory device having preamplifier with improved data propagation speed' [patent_app_type] => new [patent_app_number] => 10/270653 [patent_app_country] => US [patent_app_date] => 2002-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12233 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20030198097.pdf [firstpage_image] =>[orig_patent_app_number] => 10270653 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270653
Semiconductor memory device having preamplifier with improved data propagation speed Oct 15, 2002 Issued
Array ( [id] => 1174127 [patent_doc_number] => 06757200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Semiconductor memory having dual port cell supporting hidden refresh' [patent_app_type] => B2 [patent_app_number] => 10/269599 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4866 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757200.pdf [firstpage_image] =>[orig_patent_app_number] => 10269599 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269599
Semiconductor memory having dual port cell supporting hidden refresh Oct 9, 2002 Issued
Array ( [id] => 1234523 [patent_doc_number] => 06693838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Semiconductor memory device equipped with refresh timing signal generator' [patent_app_type] => B2 [patent_app_number] => 10/267753 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7649 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693838.pdf [firstpage_image] =>[orig_patent_app_number] => 10267753 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/267753
Semiconductor memory device equipped with refresh timing signal generator Oct 9, 2002 Issued
Array ( [id] => 1216139 [patent_doc_number] => 06711072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Digital memory circuit having a plurality of memory areas' [patent_app_type] => B2 [patent_app_number] => 10/266355 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7663 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711072.pdf [firstpage_image] =>[orig_patent_app_number] => 10266355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/266355
Digital memory circuit having a plurality of memory areas Oct 6, 2002 Issued
Array ( [id] => 7628755 [patent_doc_number] => 06819605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Semiconductor memory device and redundancy judging method' [patent_app_type] => B2 [patent_app_number] => 10/265254 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14096 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819605.pdf [firstpage_image] =>[orig_patent_app_number] => 10265254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/265254
Semiconductor memory device and redundancy judging method Oct 6, 2002 Issued
Array ( [id] => 6651962 [patent_doc_number] => 20030076730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Nonvolatile semiconductor memory device of dual-operation type with data protection function' [patent_app_type] => new [patent_app_number] => 10/263646 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5200 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20030076730.pdf [firstpage_image] =>[orig_patent_app_number] => 10263646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263646
Nonvolatile semiconductor memory device of dual-operation type with data protection function Oct 3, 2002 Issued
Array ( [id] => 1122812 [patent_doc_number] => 06798681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'DRAM' [patent_app_type] => B2 [patent_app_number] => 10/256954 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4660 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798681.pdf [firstpage_image] =>[orig_patent_app_number] => 10256954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256954
DRAM Sep 26, 2002 Issued
Array ( [id] => 6673109 [patent_doc_number] => 20030058712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Bit line control decoder circuit, virtual ground type nonvolatile semiconductor storage device provided with the decoder circuit, and data read method of virtual ground type nonvolatile semiconductor storage device' [patent_app_type] => new [patent_app_number] => 10/256255 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11633 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20030058712.pdf [firstpage_image] =>[orig_patent_app_number] => 10256255 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256255
BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH THE DECODER CIRCUIT, AND DATA READ METHOD OF VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE Sep 26, 2002 Issued
Array ( [id] => 6728851 [patent_doc_number] => 20030185041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/254648 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6343 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20030185041.pdf [firstpage_image] =>[orig_patent_app_number] => 10254648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254648
Semiconductor memory device Sep 25, 2002 Issued
Array ( [id] => 1104535 [patent_doc_number] => 06816407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor' [patent_app_type] => B2 [patent_app_number] => 10/259252 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2994 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816407.pdf [firstpage_image] =>[orig_patent_app_number] => 10259252 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/259252
Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor Sep 25, 2002 Issued
Array ( [id] => 7268778 [patent_doc_number] => 20040057296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Topography correction for testing of redundant array elements' [patent_app_type] => new [patent_app_number] => 10/253148 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20040057296.pdf [firstpage_image] =>[orig_patent_app_number] => 10253148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/253148
Topography correction for testing of redundant array elements Sep 23, 2002 Issued
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