Son Luu Mai

Array ( [id] => 1216139 [patent_doc_number] => 06711072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Digital memory circuit having a plurality of memory areas' [patent_app_type] => B2 [patent_app_number] => 10/266355 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7663 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711072.pdf [firstpage_image] =>[orig_patent_app_number] => 10266355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7628755 [patent_doc_number] => 06819605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Semiconductor memory device and redundancy judging method' [patent_app_type] => B2 [patent_app_number] => 10/265254 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14096 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819605.pdf [firstpage_image] =>[orig_patent_app_number] => 10265254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6651962 [patent_doc_number] => 20030076730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Nonvolatile semiconductor memory device of dual-operation type with data protection function' [patent_app_type] => new [patent_app_number] => 10/263646 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5200 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20030076730.pdf [firstpage_image] =>[orig_patent_app_number] => 10263646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6673109 [patent_doc_number] => 20030058712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Bit line control decoder circuit, virtual ground type nonvolatile semiconductor storage device provided with the decoder circuit, and data read method of virtual ground type nonvolatile semiconductor storage device' [patent_app_type] => new [patent_app_number] => 10/256255 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11633 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20030058712.pdf [firstpage_image] =>[orig_patent_app_number] => 10256255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1122812 [patent_doc_number] => 06798681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'DRAM' [patent_app_type] => B2 [patent_app_number] => 10/256954 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4660 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798681.pdf [firstpage_image] =>[orig_patent_app_number] => 10256954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1104535 [patent_doc_number] => 06816407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor' [patent_app_type] => B2 [patent_app_number] => 10/259252 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2994 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816407.pdf [firstpage_image] =>[orig_patent_app_number] => 10259252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6728851 [patent_doc_number] => 20030185041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/254648 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6343 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20030185041.pdf [firstpage_image] =>[orig_patent_app_number] => 10254648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7268778 [patent_doc_number] => 20040057296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Topography correction for testing of redundant array elements' [patent_app_type] => new [patent_app_number] => 10/253148 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20040057296.pdf [firstpage_image] =>[orig_patent_app_number] => 10253148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6799466 [patent_doc_number] => 20030094630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Nonvolatile ferroelectric memory device and method for driving the same' [patent_app_type] => new [patent_app_number] => 10/251848 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5009 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094630.pdf [firstpage_image] =>[orig_patent_app_number] => 10251848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1176063 [patent_doc_number] => 06754106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 10/245146 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5595 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754106.pdf [firstpage_image] =>[orig_patent_app_number] => 10245146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1212549 [patent_doc_number] => 06714459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Nonvolatile semiconductor memory device and method of detecting overerased cell' [patent_app_type] => B2 [patent_app_number] => 10/241752 [patent_app_country] => US [patent_app_date] => 2002-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 12735 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714459.pdf [firstpage_image] =>[orig_patent_app_number] => 10241752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1172748 [patent_doc_number] => 06760254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/235655 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 421 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760254.pdf [firstpage_image] =>[orig_patent_app_number] => 10235655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1223547 [patent_doc_number] => 06704241 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Memory architecture with vertical and horizontal row decoding' [patent_app_type] => B1 [patent_app_number] => 10/238048 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3716 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704241.pdf [firstpage_image] =>[orig_patent_app_number] => 10238048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7623015 [patent_doc_number] => 06687150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Reference voltage generation for memory circuits' [patent_app_type] => B1 [patent_app_number] => 10/064955 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1760 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687150.pdf [firstpage_image] =>[orig_patent_app_number] => 10064955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1212537 [patent_doc_number] => 06714457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Parallel channel programming scheme for MLC flash memory' [patent_app_type] => B1 [patent_app_number] => 10/233642 [patent_app_country] => US [patent_app_date] => 2002-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8382 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714457.pdf [firstpage_image] =>[orig_patent_app_number] => 10233642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1204608 [patent_doc_number] => 06721210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Voltage boosting circuit for a low power semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 10/232852 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5367 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721210.pdf [firstpage_image] =>[orig_patent_app_number] => 10232852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7611870 [patent_doc_number] => 06903969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'One-device non-volatile random access memory cell' [patent_app_type] => utility [patent_app_number] => 10/232848 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6938 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903969.pdf [firstpage_image] =>[orig_patent_app_number] => 10232848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6719661 [patent_doc_number] => 20030053349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Blowable memory device and method of blowing such a memory' [patent_app_type] => new [patent_app_number] => 10/233052 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3427 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053349.pdf [firstpage_image] =>[orig_patent_app_number] => 10233052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1322665 [patent_doc_number] => 06608772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-19 [patent_title] => 'Low-power semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/230213 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 28065 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/608/06608772.pdf [firstpage_image] =>[orig_patent_app_number] => 10230213 [rel_patent_id] =>[rel_patent_doc_number] =>)