
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6799466
[patent_doc_number] => 20030094630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'Nonvolatile ferroelectric memory device and method for driving the same'
[patent_app_type] => new
[patent_app_number] => 10/251848
[patent_app_country] => US
[patent_app_date] => 2002-09-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0094/20030094630.pdf
[firstpage_image] =>[orig_patent_app_number] => 10251848
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/251848 | Nonvolatile ferroelectric memory device and method for driving the same | Sep 22, 2002 | Issued |
Array
(
[id] => 1176063
[patent_doc_number] => 06754106
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-22
[patent_title] => 'Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory'
[patent_app_type] => B1
[patent_app_number] => 10/245146
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[patent_app_date] => 2002-09-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/245146 | Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory | Sep 15, 2002 | Issued |
| 10/243753 | SEMICONDUCTOR MEMORY DEVICE HAVING WORD LINES DRIVEN BY ROW SELECTING SIGNAL AND COLUMN SELECTING SIGNAL LINES ARRANGED PARALLEL TO EACH OTHER | Sep 15, 2002 | Abandoned |
Array
(
[id] => 1212549
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[patent_issue_date] => 2004-03-30
[patent_title] => 'Nonvolatile semiconductor memory device and method of detecting overerased cell'
[patent_app_type] => B2
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/241752 | Nonvolatile semiconductor memory device and method of detecting overerased cell | Sep 11, 2002 | Issued |
Array
(
[id] => 1172748
[patent_doc_number] => 06760254
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-06
[patent_title] => 'Semiconductor memory device'
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Array
(
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[patent_issue_date] => 2004-03-09
[patent_title] => 'Memory architecture with vertical and horizontal row decoding'
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Array
(
[id] => 7623015
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[patent_issue_date] => 2004-02-03
[patent_title] => 'Reference voltage generation for memory circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064955 | Reference voltage generation for memory circuits | Sep 3, 2002 | Issued |
Array
(
[id] => 1212537
[patent_doc_number] => 06714457
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[patent_issue_date] => 2004-03-30
[patent_title] => 'Parallel channel programming scheme for MLC flash memory'
[patent_app_type] => B1
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[firstpage_image] =>[orig_patent_app_number] => 10233642
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/233642 | Parallel channel programming scheme for MLC flash memory | Sep 2, 2002 | Issued |
Array
(
[id] => 1204608
[patent_doc_number] => 06721210
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-13
[patent_title] => 'Voltage boosting circuit for a low power semiconductor memory'
[patent_app_type] => B1
[patent_app_number] => 10/232852
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[firstpage_image] =>[orig_patent_app_number] => 10232852
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232852 | Voltage boosting circuit for a low power semiconductor memory | Aug 29, 2002 | Issued |
Array
(
[id] => 7611870
[patent_doc_number] => 06903969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-07
[patent_title] => 'One-device non-volatile random access memory cell'
[patent_app_type] => utility
[patent_app_number] => 10/232848
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[firstpage_image] =>[orig_patent_app_number] => 10232848
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232848 | One-device non-volatile random access memory cell | Aug 29, 2002 | Issued |
Array
(
[id] => 6719661
[patent_doc_number] => 20030053349
[patent_country] => US
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[patent_issue_date] => 2003-03-20
[patent_title] => 'Blowable memory device and method of blowing such a memory'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/233052 | Blowable memory device and method of blowing such a memory | Aug 29, 2002 | Issued |
Array
(
[id] => 7131770
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[patent_title] => 'Method and apparatus for latency specific duty cycle correction'
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Array
(
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Array
(
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[patent_title] => 'Delay lock loop circuit useful in a synchronous system and associated methods'
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Array
(
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[patent_title] => 'Antifuse memory cell and antifuse memory cell array'
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Array
(
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Array
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Array
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Array
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Array
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