Son Luu Mai

Array ( [id] => 1183142 [patent_doc_number] => 06744654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'High density dynamic ternary-CAM memory architecture' [patent_app_type] => B2 [patent_app_number] => 10/224452 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3152 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744654.pdf [firstpage_image] =>[orig_patent_app_number] => 10224452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1249647 [patent_doc_number] => 06674671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Circuit for lines with multiple drivers' [patent_app_type] => B1 [patent_app_number] => 10/218348 [patent_app_country] => US [patent_app_date] => 2002-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5696 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674671.pdf [firstpage_image] =>[orig_patent_app_number] => 10218348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1319830 [patent_doc_number] => 06611467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => B2 [patent_app_number] => 10/212903 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3170 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611467.pdf [firstpage_image] =>[orig_patent_app_number] => 10212903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1227315 [patent_doc_number] => 06700818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method for operating a memory device' [patent_app_type] => B2 [patent_app_number] => 10/211248 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2933 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700818.pdf [firstpage_image] =>[orig_patent_app_number] => 10211248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1288414 [patent_doc_number] => 06643216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Asynchronous queuing circuit for DRAM external RAS accesses' [patent_app_type] => B1 [patent_app_number] => 10/211952 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4001 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643216.pdf [firstpage_image] =>[orig_patent_app_number] => 10211952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1406573 [patent_doc_number] => 06549442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Hardware-assisted fast bank-swap in a content-addressable-memory (CAM) processor' [patent_app_type] => B1 [patent_app_number] => 10/064554 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549442.pdf [firstpage_image] =>[orig_patent_app_number] => 10064554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416944 [patent_doc_number] => 06538939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Memory employing multiple enable/disable modes for redundant elements and testing method using same' [patent_app_type] => B1 [patent_app_number] => 10/197991 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4692 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538939.pdf [firstpage_image] =>[orig_patent_app_number] => 10197991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1275787 [patent_doc_number] => 06654282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/197646 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 8282 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654282.pdf [firstpage_image] =>[orig_patent_app_number] => 10197646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7352399 [patent_doc_number] => 20040013004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Lower power consuming sense amplifier' [patent_app_type] => new [patent_app_number] => 10/198454 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1418 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20040013004.pdf [firstpage_image] =>[orig_patent_app_number] => 10198454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1216109 [patent_doc_number] => 06711062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Erase method of split gate flash memory reference cells' [patent_app_type] => B1 [patent_app_number] => 10/197049 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1988 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711062.pdf [firstpage_image] =>[orig_patent_app_number] => 10197049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1303621 [patent_doc_number] => 06628537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems' [patent_app_type] => B1 [patent_app_number] => 10/197027 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6790 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/628/06628537.pdf [firstpage_image] =>[orig_patent_app_number] => 10197027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6734431 [patent_doc_number] => 20030012066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Memory and method for replacing defective memory cells in the same' [patent_app_type] => new [patent_app_number] => 10/195753 [patent_app_country] => US [patent_app_date] => 2002-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5844 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20030012066.pdf [firstpage_image] =>[orig_patent_app_number] => 10195753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1174092 [patent_doc_number] => 06757195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Flash memory having enhanced yield and having enhanced reliability in redundant and dummy circuits' [patent_app_type] => B2 [patent_app_number] => 10/193252 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7684 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757195.pdf [firstpage_image] =>[orig_patent_app_number] => 10193252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7360461 [patent_doc_number] => 20040004896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'DYNAMIC INPUT THRESHOLDS FOR SEMICONDUCTOR DEVICES' [patent_app_type] => new [patent_app_number] => 10/190648 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1954 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004896.pdf [firstpage_image] =>[orig_patent_app_number] => 10190648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7360254 [patent_doc_number] => 20040004860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Column decode circuit for high density/high performance memories' [patent_app_type] => new [patent_app_number] => 10/190650 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5478 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004860.pdf [firstpage_image] =>[orig_patent_app_number] => 10190650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6435781 [patent_doc_number] => 20020176303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Device and method for repairing a memory array by storing each bit in multiple memory cells in the array' [patent_app_type] => new [patent_app_number] => 10/189138 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8219 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20020176303.pdf [firstpage_image] =>[orig_patent_app_number] => 10189138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6773235 [patent_doc_number] => 20030016573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Non-volatile semiconductor memory device and information apparatus' [patent_app_type] => new [patent_app_number] => 10/187048 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9950 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20030016573.pdf [firstpage_image] =>[orig_patent_app_number] => 10187048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6734430 [patent_doc_number] => 20030012065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Burst mode receiving apparatus having an offset compensating function and a data recovery method thereof' [patent_app_type] => new [patent_app_number] => 10/183046 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6453 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20030012065.pdf [firstpage_image] =>[orig_patent_app_number] => 10183046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6754575 [patent_doc_number] => 20030002351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Integrated memory circuit and method for reading a data item from a memory cell' [patent_app_type] => new [patent_app_number] => 10/178646 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4675 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002351.pdf [firstpage_image] =>[orig_patent_app_number] => 10178646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6714777 [patent_doc_number] => 20030026125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Thin film magnetic memory device including memory cells having a magnetic tunnel junction' [patent_app_type] => new [patent_app_number] => 10/175846 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 23928 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20030026125.pdf [firstpage_image] =>[orig_patent_app_number] => 10175846 [rel_patent_id] =>[rel_patent_doc_number] =>)