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Son Luu Mai

Examiner (ID: 18155)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818
Total Applications
3063
Issued Applications
2917
Pending Applications
45
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7963111 [patent_doc_number] => 06680874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Delay lock loop circuit useful in a synchronous system and associated methods' [patent_app_type] => B1 [patent_app_number] => 10/230750 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 14840 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680874.pdf [firstpage_image] =>[orig_patent_app_number] => 10230750 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230750
Delay lock loop circuit useful in a synchronous system and associated methods Aug 28, 2002 Issued
Array ( [id] => 7131770 [patent_doc_number] => 20040042255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method and apparatus for latency specific duty cycle correction' [patent_app_type] => new [patent_app_number] => 10/230546 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3704 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042255.pdf [firstpage_image] =>[orig_patent_app_number] => 10230546 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230546
Method and apparatus for latency specific duty cycle correction Aug 28, 2002 Issued
Array ( [id] => 6749131 [patent_doc_number] => 20030043651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Semiconductor storage device and setting method thereof' [patent_app_type] => new [patent_app_number] => 10/229147 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10067 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20030043651.pdf [firstpage_image] =>[orig_patent_app_number] => 10229147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229147
Semiconductor storage device and setting method thereof Aug 27, 2002 Issued
Array ( [id] => 1204587 [patent_doc_number] => 06721197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Antifuse memory cell and antifuse memory cell array' [patent_app_type] => B1 [patent_app_number] => 10/231655 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3347 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721197.pdf [firstpage_image] =>[orig_patent_app_number] => 10231655 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231655
Antifuse memory cell and antifuse memory cell array Aug 27, 2002 Issued
Array ( [id] => 1376904 [patent_doc_number] => 06570798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Antifuse memory cell and antifuse memory cell array' [patent_app_type] => B1 [patent_app_number] => 10/231708 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3338 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570798.pdf [firstpage_image] =>[orig_patent_app_number] => 10231708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231708
Antifuse memory cell and antifuse memory cell array Aug 27, 2002 Issued
Array ( [id] => 1042107 [patent_doc_number] => 06870757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Thin film magnetic memory device applying a magnetic field to write data' [patent_app_type] => utility [patent_app_number] => 10/227452 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 0 [patent_no_of_words] => 11898 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870757.pdf [firstpage_image] =>[orig_patent_app_number] => 10227452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227452
Thin film magnetic memory device applying a magnetic field to write data Aug 25, 2002 Issued
Array ( [id] => 994834 [patent_doc_number] => 06917546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Memory device and memory system' [patent_app_type] => utility [patent_app_number] => 10/227647 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8136 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917546.pdf [firstpage_image] =>[orig_patent_app_number] => 10227647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227647
Memory device and memory system Aug 22, 2002 Issued
Array ( [id] => 1140238 [patent_doc_number] => 06785186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Design of an high speed xdecoder driving a large wordline load consuming less switching current for use in high speed syncflash memory' [patent_app_type] => B2 [patent_app_number] => 10/224451 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2428 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785186.pdf [firstpage_image] =>[orig_patent_app_number] => 10224451 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224451
Design of an high speed xdecoder driving a large wordline load consuming less switching current for use in high speed syncflash memory Aug 20, 2002 Issued
Array ( [id] => 1183142 [patent_doc_number] => 06744654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'High density dynamic ternary-CAM memory architecture' [patent_app_type] => B2 [patent_app_number] => 10/224452 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3152 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744654.pdf [firstpage_image] =>[orig_patent_app_number] => 10224452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224452
High density dynamic ternary-CAM memory architecture Aug 20, 2002 Issued
Array ( [id] => 1249647 [patent_doc_number] => 06674671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Circuit for lines with multiple drivers' [patent_app_type] => B1 [patent_app_number] => 10/218348 [patent_app_country] => US [patent_app_date] => 2002-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5696 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674671.pdf [firstpage_image] =>[orig_patent_app_number] => 10218348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/218348
Circuit for lines with multiple drivers Aug 13, 2002 Issued
Array ( [id] => 1319830 [patent_doc_number] => 06611467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines' [patent_app_type] => B2 [patent_app_number] => 10/212903 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3170 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611467.pdf [firstpage_image] =>[orig_patent_app_number] => 10212903 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212903
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines Aug 4, 2002 Issued
Array ( [id] => 1227315 [patent_doc_number] => 06700818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method for operating a memory device' [patent_app_type] => B2 [patent_app_number] => 10/211248 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2933 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700818.pdf [firstpage_image] =>[orig_patent_app_number] => 10211248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/211248
Method for operating a memory device Aug 4, 2002 Issued
Array ( [id] => 1288414 [patent_doc_number] => 06643216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Asynchronous queuing circuit for DRAM external RAS accesses' [patent_app_type] => B1 [patent_app_number] => 10/211952 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4001 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643216.pdf [firstpage_image] =>[orig_patent_app_number] => 10211952 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/211952
Asynchronous queuing circuit for DRAM external RAS accesses Aug 1, 2002 Issued
Array ( [id] => 1406573 [patent_doc_number] => 06549442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Hardware-assisted fast bank-swap in a content-addressable-memory (CAM) processor' [patent_app_type] => B1 [patent_app_number] => 10/064554 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549442.pdf [firstpage_image] =>[orig_patent_app_number] => 10064554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064554
Hardware-assisted fast bank-swap in a content-addressable-memory (CAM) processor Jul 24, 2002 Issued
Array ( [id] => 1275787 [patent_doc_number] => 06654282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/197646 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 8282 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654282.pdf [firstpage_image] =>[orig_patent_app_number] => 10197646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197646
Nonvolatile semiconductor memory device Jul 17, 2002 Issued
Array ( [id] => 7352399 [patent_doc_number] => 20040013004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Lower power consuming sense amplifier' [patent_app_type] => new [patent_app_number] => 10/198454 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1418 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20040013004.pdf [firstpage_image] =>[orig_patent_app_number] => 10198454 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/198454
Lower power consuming sense amplifier Jul 17, 2002 Abandoned
Array ( [id] => 1416944 [patent_doc_number] => 06538939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Memory employing multiple enable/disable modes for redundant elements and testing method using same' [patent_app_type] => B1 [patent_app_number] => 10/197991 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4692 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538939.pdf [firstpage_image] =>[orig_patent_app_number] => 10197991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197991
Memory employing multiple enable/disable modes for redundant elements and testing method using same Jul 17, 2002 Issued
Array ( [id] => 1216109 [patent_doc_number] => 06711062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Erase method of split gate flash memory reference cells' [patent_app_type] => B1 [patent_app_number] => 10/197049 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1988 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711062.pdf [firstpage_image] =>[orig_patent_app_number] => 10197049 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197049
Erase method of split gate flash memory reference cells Jul 16, 2002 Issued
Array ( [id] => 1303621 [patent_doc_number] => 06628537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems' [patent_app_type] => B1 [patent_app_number] => 10/197027 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6790 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/628/06628537.pdf [firstpage_image] =>[orig_patent_app_number] => 10197027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197027
Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems Jul 15, 2002 Issued
Array ( [id] => 6734431 [patent_doc_number] => 20030012066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Memory and method for replacing defective memory cells in the same' [patent_app_type] => new [patent_app_number] => 10/195753 [patent_app_country] => US [patent_app_date] => 2002-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5844 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20030012066.pdf [firstpage_image] =>[orig_patent_app_number] => 10195753 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/195753
Memory and method for replacing defective memory cells in the same Jul 14, 2002 Abandoned
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