
Son Luu Mai
Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2511, 2827 |
| Total Applications | 3061 |
| Issued Applications | 2917 |
| Pending Applications | 43 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6546984
[patent_doc_number] => 20020163847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-07
[patent_title] => 'Dynamic random access memory with low power consumption'
[patent_app_type] => new
[patent_app_number] => 10/175859
[patent_app_country] => US
[patent_app_date] => 2002-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3625
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[pdf_file] => publications/A1/0163/20020163847.pdf
[firstpage_image] =>[orig_patent_app_number] => 10175859
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/175859 | Dynamic random access memory with low power consumption | Jun 20, 2002 | Issued |
Array
(
[id] => 1227317
[patent_doc_number] => 06700819
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-02
[patent_title] => 'Memory with improved differential reading system'
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[patent_app_number] => 10/176954
[patent_app_country] => US
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[pdf_file] => patents/06/700/06700819.pdf
[firstpage_image] =>[orig_patent_app_number] => 10176954
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/176954 | Memory with improved differential reading system | Jun 19, 2002 | Issued |
Array
(
[id] => 6644175
[patent_doc_number] => 20030007404
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'Sense amplifier circuit'
[patent_app_type] => new
[patent_app_number] => 10/173155
[patent_app_country] => US
[patent_app_date] => 2002-06-18
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[firstpage_image] =>[orig_patent_app_number] => 10173155
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/173155 | Sense amplifier circuit | Jun 17, 2002 | Issued |
Array
(
[id] => 1140168
[patent_doc_number] => 06785167
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-31
[patent_title] => 'ROM embedded DRAM with programming'
[patent_app_type] => B2
[patent_app_number] => 10/174746
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10174746
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/174746 | ROM embedded DRAM with programming | Jun 17, 2002 | Issued |
Array
(
[id] => 1334623
[patent_doc_number] => 06600675
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-29
[patent_title] => 'Reference circuit in ferroelectric memory and method for driving the same'
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[patent_app_number] => 10/170646
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[pdf_file] => patents/06/600/06600675.pdf
[firstpage_image] =>[orig_patent_app_number] => 10170646
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/170646 | Reference circuit in ferroelectric memory and method for driving the same | Jun 13, 2002 | Issued |
Array
(
[id] => 1349975
[patent_doc_number] => 06590801
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-08
[patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures'
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[patent_app_number] => 10/172106
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[firstpage_image] =>[orig_patent_app_number] => 10172106
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172106 | Current leakage reduction for loaded bit-lines in on-chip memory structures | Jun 12, 2002 | Issued |
Array
(
[id] => 1427758
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[patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures'
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[pdf_file] => patents/06/519/06519178.pdf
[firstpage_image] =>[orig_patent_app_number] => 10172107
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172107 | Current leakage reduction for loaded bit-lines in on-chip memory structures | Jun 12, 2002 | Issued |
Array
(
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[patent_doc_number] => 06614680
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[patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures'
[patent_app_type] => B2
[patent_app_number] => 10/172277
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[pdf_file] => patents/06/614/06614680.pdf
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Array
(
[id] => 1426110
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[patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures'
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Array
(
[id] => 6754550
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[patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172234 | Current leakage reduction for loaded bit-lines in on-chip memory structures | Jun 12, 2002 | Abandoned |
Array
(
[id] => 6695722
[patent_doc_number] => 20030107916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-12
[patent_title] => 'THIN FILM MAGNETIC MEMORY DEVICE CONDUCTING DATA READ OPERATION WITHOUT USING A REFERENCE CELL'
[patent_app_type] => new
[patent_app_number] => 10/164548
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0107/20030107916.pdf
[firstpage_image] =>[orig_patent_app_number] => 10164548
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/164548 | Thin film magnetic memory device conducting data read operation without using a reference cell | Jun 9, 2002 | Issued |
Array
(
[id] => 1285480
[patent_doc_number] => 06646944
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-11
[patent_title] => 'Semiconductor memory device'
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[patent_app_number] => 10/164651
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[firstpage_image] =>[orig_patent_app_number] => 10164651
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/164651 | Semiconductor memory device | Jun 9, 2002 | Issued |
Array
(
[id] => 1342050
[patent_doc_number] => 06597608
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-22
[patent_title] => 'CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN'
[patent_app_type] => B2
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[firstpage_image] =>[orig_patent_app_number] => 10163351
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/163351 | CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN | Jun 6, 2002 | Issued |
Array
(
[id] => 1247691
[patent_doc_number] => 06678184
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[patent_issue_date] => 2004-01-13
[patent_title] => 'CAM cell having compare circuit formed over two active regions'
[patent_app_type] => B2
[patent_app_number] => 10/163848
[patent_app_country] => US
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Array
(
[id] => 1538560
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[patent_title] => 'Method for operating a nonvolatile memory having embedded word lines'
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Array
(
[id] => 6754599
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[patent_issue_date] => 2003-01-02
[patent_title] => 'Memory arrangement'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/161146 | Memory arrangement with selectable memory sectors | May 30, 2002 | Issued |
Array
(
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[patent_doc_number] => 06788586
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[patent_title] => 'Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/159152 | Non-volatile delay register | May 28, 2002 | Issued |
Array
(
[id] => 1275827
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[patent_title] => 'Electrically erasable programmable read-only memory and method of erasing select memory cells'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/155953 | Electrically erasable programmable read-only memory and method of erasing select memory cells | May 23, 2002 | Issued |
Array
(
[id] => 6820737
[patent_doc_number] => 20030218898
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[patent_issue_date] => 2003-11-27
[patent_title] => 'GROUPED PLATE LINE DRIVE ARCHITECTURE AND METHOD'
[patent_app_type] => new
[patent_app_number] => 10/154647
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/154647 | Grouped plate line drive architecture and method | May 23, 2002 | Issued |