Search

Son Luu Mai

Examiner (ID: 6998, Phone: (571)272-1786 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2511, 2827
Total Applications
3061
Issued Applications
2917
Pending Applications
43
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6546984 [patent_doc_number] => 20020163847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Dynamic random access memory with low power consumption' [patent_app_type] => new [patent_app_number] => 10/175859 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3625 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20020163847.pdf [firstpage_image] =>[orig_patent_app_number] => 10175859 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/175859
Dynamic random access memory with low power consumption Jun 20, 2002 Issued
Array ( [id] => 1227317 [patent_doc_number] => 06700819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Memory with improved differential reading system' [patent_app_type] => B2 [patent_app_number] => 10/176954 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6406 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700819.pdf [firstpage_image] =>[orig_patent_app_number] => 10176954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/176954
Memory with improved differential reading system Jun 19, 2002 Issued
Array ( [id] => 6644175 [patent_doc_number] => 20030007404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Sense amplifier circuit' [patent_app_type] => new [patent_app_number] => 10/173155 [patent_app_country] => US [patent_app_date] => 2002-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2847 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007404.pdf [firstpage_image] =>[orig_patent_app_number] => 10173155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173155
Sense amplifier circuit Jun 17, 2002 Issued
Array ( [id] => 1140168 [patent_doc_number] => 06785167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'ROM embedded DRAM with programming' [patent_app_type] => B2 [patent_app_number] => 10/174746 [patent_app_country] => US [patent_app_date] => 2002-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3609 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785167.pdf [firstpage_image] =>[orig_patent_app_number] => 10174746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/174746
ROM embedded DRAM with programming Jun 17, 2002 Issued
Array ( [id] => 1334623 [patent_doc_number] => 06600675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Reference circuit in ferroelectric memory and method for driving the same' [patent_app_type] => B2 [patent_app_number] => 10/170646 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5340 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600675.pdf [firstpage_image] =>[orig_patent_app_number] => 10170646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/170646
Reference circuit in ferroelectric memory and method for driving the same Jun 13, 2002 Issued
Array ( [id] => 1349975 [patent_doc_number] => 06590801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures' [patent_app_type] => B2 [patent_app_number] => 10/172106 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1942 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590801.pdf [firstpage_image] =>[orig_patent_app_number] => 10172106 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172106
Current leakage reduction for loaded bit-lines in on-chip memory structures Jun 12, 2002 Issued
Array ( [id] => 1427758 [patent_doc_number] => 06519178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures' [patent_app_type] => B2 [patent_app_number] => 10/172107 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1936 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519178.pdf [firstpage_image] =>[orig_patent_app_number] => 10172107 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172107
Current leakage reduction for loaded bit-lines in on-chip memory structures Jun 12, 2002 Issued
Array ( [id] => 1319098 [patent_doc_number] => 06614680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures' [patent_app_type] => B2 [patent_app_number] => 10/172277 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1936 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614680.pdf [firstpage_image] =>[orig_patent_app_number] => 10172277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172277
Current leakage reduction for loaded bit-lines in on-chip memory structures Jun 12, 2002 Issued
Array ( [id] => 1426110 [patent_doc_number] => 06510077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures' [patent_app_type] => B1 [patent_app_number] => 10/172233 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1935 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510077.pdf [firstpage_image] =>[orig_patent_app_number] => 10172233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172233
Current leakage reduction for loaded bit-lines in on-chip memory structures Jun 12, 2002 Issued
Array ( [id] => 6754550 [patent_doc_number] => 20030002326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Current leakage reduction for loaded bit-lines in on-chip memory structures' [patent_app_type] => new [patent_app_number] => 10/172234 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1963 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002326.pdf [firstpage_image] =>[orig_patent_app_number] => 10172234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172234
Current leakage reduction for loaded bit-lines in on-chip memory structures Jun 12, 2002 Abandoned
Array ( [id] => 6695722 [patent_doc_number] => 20030107916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'THIN FILM MAGNETIC MEMORY DEVICE CONDUCTING DATA READ OPERATION WITHOUT USING A REFERENCE CELL' [patent_app_type] => new [patent_app_number] => 10/164548 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12526 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107916.pdf [firstpage_image] =>[orig_patent_app_number] => 10164548 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164548
Thin film magnetic memory device conducting data read operation without using a reference cell Jun 9, 2002 Issued
Array ( [id] => 1285480 [patent_doc_number] => 06646944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/164651 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 55 [patent_no_of_words] => 32698 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646944.pdf [firstpage_image] =>[orig_patent_app_number] => 10164651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164651
Semiconductor memory device Jun 9, 2002 Issued
Array ( [id] => 1342050 [patent_doc_number] => 06597608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN' [patent_app_type] => B2 [patent_app_number] => 10/163351 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 9667 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597608.pdf [firstpage_image] =>[orig_patent_app_number] => 10163351 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163351
CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN Jun 6, 2002 Issued
Array ( [id] => 1247691 [patent_doc_number] => 06678184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'CAM cell having compare circuit formed over two active regions' [patent_app_type] => B2 [patent_app_number] => 10/163848 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5520 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678184.pdf [firstpage_image] =>[orig_patent_app_number] => 10163848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163848
CAM cell having compare circuit formed over two active regions Jun 4, 2002 Issued
Array ( [id] => 1538560 [patent_doc_number] => 06490196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method for operating a nonvolatile memory having embedded word lines' [patent_app_type] => B1 [patent_app_number] => 10/064047 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3083 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490196.pdf [firstpage_image] =>[orig_patent_app_number] => 10064047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064047
Method for operating a nonvolatile memory having embedded word lines Jun 3, 2002 Issued
Array ( [id] => 6754599 [patent_doc_number] => 20030002375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Memory arrangement' [patent_app_type] => new [patent_app_number] => 10/161146 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2382 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002375.pdf [firstpage_image] =>[orig_patent_app_number] => 10161146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161146
Memory arrangement with selectable memory sectors May 30, 2002 Issued
Array ( [id] => 1135683 [patent_doc_number] => 06788586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same' [patent_app_type] => B2 [patent_app_number] => 10/161053 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4171 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788586.pdf [firstpage_image] =>[orig_patent_app_number] => 10161053 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161053
Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same May 29, 2002 Issued
Array ( [id] => 1310753 [patent_doc_number] => 06621762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Non-volatile delay register' [patent_app_type] => B1 [patent_app_number] => 10/159152 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2723 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621762.pdf [firstpage_image] =>[orig_patent_app_number] => 10159152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159152
Non-volatile delay register May 28, 2002 Issued
Array ( [id] => 1275827 [patent_doc_number] => 06654291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Electrically erasable programmable read-only memory and method of erasing select memory cells' [patent_app_type] => B2 [patent_app_number] => 10/155953 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654291.pdf [firstpage_image] =>[orig_patent_app_number] => 10155953 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155953
Electrically erasable programmable read-only memory and method of erasing select memory cells May 23, 2002 Issued
Array ( [id] => 6820737 [patent_doc_number] => 20030218898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'GROUPED PLATE LINE DRIVE ARCHITECTURE AND METHOD' [patent_app_type] => new [patent_app_number] => 10/154647 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3119 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218898.pdf [firstpage_image] =>[orig_patent_app_number] => 10154647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154647
Grouped plate line drive architecture and method May 23, 2002 Issued
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