Son T. Dinh

Array ( [id] => 6063513 [patent_doc_number] => 20020031846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Method and device for manufacturing ceramics, semiconductor device and piezoelectric device' [patent_app_type] => new [patent_app_number] => 09/819687 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6063 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031846.pdf [firstpage_image] =>[orig_patent_app_number] => 09819687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6886613 [patent_doc_number] => 20010019882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Method of making electrical interconnection for attachment to a substrate' [patent_app_type] => new [patent_app_number] => 09/817877 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3394 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019882.pdf [firstpage_image] =>[orig_patent_app_number] => 09817877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6921596 [patent_doc_number] => 20010029081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Method for producing semiconductor device' [patent_app_type] => new [patent_app_number] => 09/815037 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5418 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029081.pdf [firstpage_image] =>[orig_patent_app_number] => 09815037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1367559 [patent_doc_number] => 06566242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Dual damascene copper interconnect to a damascene tungsten wiring level' [patent_app_type] => B1 [patent_app_number] => 09/816977 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6604 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566242.pdf [firstpage_image] =>[orig_patent_app_number] => 09816977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1315593 [patent_doc_number] => 06607982 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'High magnesium content copper magnesium alloys as diffusion barriers' [patent_app_type] => B1 [patent_app_number] => 09/816847 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607982.pdf [firstpage_image] =>[orig_patent_app_number] => 09816847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1379511 [patent_doc_number] => 06555472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method of producing a semiconductor device using feature trimming' [patent_app_type] => B2 [patent_app_number] => 09/816877 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2979 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555472.pdf [firstpage_image] =>[orig_patent_app_number] => 09816877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6894039 [patent_doc_number] => 20010016405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Unique via patterning scheme which utilizes hard mask cap for low dielectric constant materials' [patent_app_type] => new [patent_app_number] => 09/808758 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3249 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20010016405.pdf [firstpage_image] =>[orig_patent_app_number] => 09808758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1310703 [patent_doc_number] => 06613652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance' [patent_app_type] => B2 [patent_app_number] => 09/805707 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3712 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613652.pdf [firstpage_image] =>[orig_patent_app_number] => 09805707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297470 [patent_doc_number] => 06627526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method for fabricating a conductive structure for a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/805287 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2465 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627526.pdf [firstpage_image] =>[orig_patent_app_number] => 09805287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1362082 [patent_doc_number] => 06569768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'Surface treatment and capping layer process for producing a copper interface in a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/804657 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2966 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569768.pdf [firstpage_image] =>[orig_patent_app_number] => 09804657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1324469 [patent_doc_number] => 06602794 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Silylation process for forming contacts' [patent_app_type] => B1 [patent_app_number] => 09/802437 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602794.pdf [firstpage_image] =>[orig_patent_app_number] => 09802437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6379124 [patent_doc_number] => 20020119654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Method for dual-damascene patterning of low-k interconnects using spin-on distributed hardmask' [patent_app_type] => new [patent_app_number] => 09/795417 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3691 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20020119654.pdf [firstpage_image] =>[orig_patent_app_number] => 09795417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6892097 [patent_doc_number] => 20010018259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Method for fabricating conductive line pattern for semiconductor device' [patent_app_type] => new [patent_app_number] => 09/793567 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2298 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20010018259.pdf [firstpage_image] =>[orig_patent_app_number] => 09793567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1595815 [patent_doc_number] => 06492283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method of forming ultrathin oxide layer' [patent_app_type] => B2 [patent_app_number] => 09/791167 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3706 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492283.pdf [firstpage_image] =>[orig_patent_app_number] => 09791167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1336708 [patent_doc_number] => 06593253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/763127 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3950 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593253.pdf [firstpage_image] =>[orig_patent_app_number] => 09763127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7631367 [patent_doc_number] => 06635565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method of cleaning a dual damascene structure' [patent_app_type] => B2 [patent_app_number] => 09/789357 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2009 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635565.pdf [firstpage_image] =>[orig_patent_app_number] => 09789357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6896212 [patent_doc_number] => 20010027002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method for forming multi-layered interconnect structure' [patent_app_type] => new [patent_app_number] => 09/784267 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4255 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027002.pdf [firstpage_image] =>[orig_patent_app_number] => 09784267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6548029 [patent_doc_number] => 20020110999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Reliable interconnects with low via/contact resistance' [patent_app_type] => new [patent_app_number] => 09/783157 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2337 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20020110999.pdf [firstpage_image] =>[orig_patent_app_number] => 09783157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1440003 [patent_doc_number] => 06495402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture' [patent_app_type] => B1 [patent_app_number] => 09/777637 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2841 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495402.pdf [firstpage_image] =>[orig_patent_app_number] => 09777637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6277178 [patent_doc_number] => 20020106876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Method of forming a buffer layer over a polysilicon gate' [patent_app_type] => new [patent_app_number] => 09/776737 [patent_app_country] => US [patent_app_date] => 2001-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2806 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106876.pdf [firstpage_image] =>[orig_patent_app_number] => 09776737 [rel_patent_id] =>[rel_patent_doc_number] =>)