Search

Son T. Dinh

Examiner (ID: 17141, Phone: (571)272-1868 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2824, 2511, 2502
Total Applications
3088
Issued Applications
2939
Pending Applications
71
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19531474 [patent_doc_number] => 20240355376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => PRE-CHARGE CONTROL CIRCUIT AND VOLTAGE GENERATION CIRCUIT INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/454449 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/454449
Pre-charge control circuit and voltage generation circuit including the same Aug 22, 2023 Issued
Array ( [id] => 20132086 [patent_doc_number] => 12374403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Optimized read current consumption based on lower page read information for non-volatile memory apparatus [patent_app_type] => utility [patent_app_number] => 18/229748 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 13668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229748 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229748
Optimized read current consumption based on lower page read information for non-volatile memory apparatus Aug 2, 2023 Issued
Array ( [id] => 20530185 [patent_doc_number] => 12548626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Positive sensing in low power operation mode in a memory device [patent_app_type] => utility [patent_app_number] => 18/228406 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 8431 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228406
Positive sensing in low power operation mode in a memory device Jul 30, 2023 Issued
Array ( [id] => 19007450 [patent_doc_number] => 20240071521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY DEVICE PRODUCING METADATA CHARACTERIZING APPLIED READ VOLTAGE LEVEL WITH RESPECT TO VOLTAGE DISTRIBUTIONS [patent_app_type] => utility [patent_app_number] => 18/228291 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228291 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228291
Memory device producing metadata characterizing applied read voltage level with respect to voltage distributions Jul 30, 2023 Issued
Array ( [id] => 18774023 [patent_doc_number] => 20230368853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD OF PROGRAMMING MULTI-PLANE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/227505 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227505
Method of programming multi-plane memory device Jul 27, 2023 Issued
Array ( [id] => 20118222 [patent_doc_number] => 12367937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Binary read-based fast algorithm for optimal read level acquisition [patent_app_type] => utility [patent_app_number] => 18/227581 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 7219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227581 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227581
Binary read-based fast algorithm for optimal read level acquisition Jul 27, 2023 Issued
Array ( [id] => 19828586 [patent_doc_number] => 12249377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Apparatuses and methods for organizing data in a memory device [patent_app_type] => utility [patent_app_number] => 18/225574 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225574
Apparatuses and methods for organizing data in a memory device Jul 23, 2023 Issued
Array ( [id] => 19814000 [patent_doc_number] => 12245430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Three-dimensional vertical nor flash thin-film transistor strings [patent_app_type] => utility [patent_app_number] => 18/223994 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 25189 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223994
Three-dimensional vertical nor flash thin-film transistor strings Jul 18, 2023 Issued
Array ( [id] => 19452406 [patent_doc_number] => 20240312536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORIES AND OPERATION METHODS THEREOF, MEMORY SYSTEMS AND ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/354393 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354393
MEMORIES AND OPERATION METHODS THEREOF, MEMORY SYSTEMS AND ELECTRONIC DEVICES Jul 17, 2023 Issued
Array ( [id] => 20359950 [patent_doc_number] => 12475954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Memory device including page buffer circuit and SSD including the memory device, and method of using the same [patent_app_type] => utility [patent_app_number] => 18/223278 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223278
Memory device including page buffer circuit and SSD including the memory device, and method of using the same Jul 17, 2023 Issued
Array ( [id] => 19886681 [patent_doc_number] => 12272405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Non-volatile semiconductor memory device and memory system [patent_app_type] => utility [patent_app_number] => 18/352537 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 8275 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352537
Non-volatile semiconductor memory device and memory system Jul 13, 2023 Issued
Array ( [id] => 19116145 [patent_doc_number] => 20240127895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => NON-VOLATILE MEMORY WITH OVERDRIVE VOLTAGE ZONING TO COMPENSATE FOR REDUCED MARGINS [patent_app_type] => utility [patent_app_number] => 18/351179 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351179 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351179
Non-volatile memory with overdrive voltage zoning to compensate for reduced margins Jul 11, 2023 Issued
Array ( [id] => 18905771 [patent_doc_number] => 20240021256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => ONE TIME PROGRAMMING MEMORY CELL WITH FIN FIELD-EFFECT TRANSISTOR USING PHYSICALLY UNCLONABLE FUNCTION TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 18/219864 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219864
One time programming memory cell with fin field-effect transistor using physically unclonable function technology Jul 9, 2023 Issued
Array ( [id] => 18774018 [patent_doc_number] => 20230368848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/348570 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 511 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348570
Semiconductor memory device Jul 6, 2023 Issued
Array ( [id] => 18729076 [patent_doc_number] => 20230343371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/347517 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347517 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347517
Semiconductor device Jul 4, 2023 Issued
Array ( [id] => 19980641 [patent_doc_number] => 12348132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Stage based frequency optimization for area reduction of charge pumps [patent_app_type] => utility [patent_app_number] => 18/346335 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 15640 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346335
Stage based frequency optimization for area reduction of charge pumps Jul 2, 2023 Issued
Array ( [id] => 18743112 [patent_doc_number] => 20230352100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MEMORY DEVICE AND ASYNCHRONOUS MULTI-PLANE INDEPENDENT READ OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/217987 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217987 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217987
Memory device and asynchronous multi-plane independent read operation thereof Jul 2, 2023 Issued
Array ( [id] => 19392522 [patent_doc_number] => 20240282392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => ENHANCED OPERATIONS OF NON-VOLATILE MEMORY WITH SHARED DATA TRANSFER LATCHES [patent_app_type] => utility [patent_app_number] => 18/346332 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346332 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346332
Enhanced operations of non-volatile memory with shared data transfer latches Jul 2, 2023 Issued
Array ( [id] => 19979999 [patent_doc_number] => 12347485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Establishing bitline, wordline and boost voltages to manage a maximum program voltage level during all levels programming of a memory device [patent_app_type] => utility [patent_app_number] => 18/214080 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/214080
Establishing bitline, wordline and boost voltages to manage a maximum program voltage level during all levels programming of a memory device Jun 25, 2023 Issued
Array ( [id] => 19459960 [patent_doc_number] => 12100462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Memory device and multi-pass program operation thereof [patent_app_type] => utility [patent_app_number] => 18/211495 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211495 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211495
Memory device and multi-pass program operation thereof Jun 18, 2023 Issued
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